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1. 发明授权

US08473881B1 Multi-resource aware partitioning for integrated circuits 有权
标题翻译：集成电路的多资源感知分区
公开(公告)号：US08473881B1
公开(公告)日：2013-06-25
申请号：US13007780
申请日：2011-01-17
申请人： Wei Mark Fang , Vishal Suthar , Srinivasan Dasasathyan
发明人： Wei Mark Fang , Vishal Suthar , Srinivasan Dasasathyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5072
摘要： A method of partitioning a circuit design can include identifying a circuit design in which components of the circuit design are assigned to each of a plurality of regions, wherein each region corresponds to a physical portion of an integrated circuit. A maximum oversubscription region can be determined for a selected component type from the plurality of regions. A target region from the plurality of regions can be selected that is adjacent to the region of maximum oversubscription. The method also can include re-assigning, by a processor, a selected number of components of the maximum oversubscription region to the target region.
摘要翻译：分割电路设计的方法可以包括识别其中电路设计的组件被分配给多个区域中的每一个的电路设计，其中每个区域对应于集成电路的物理部分。可以从多个区域中针对所选择的组件类型确定最大超额预订区域。来自多个区域的目标区域可以被选择为与最大超额预订区域相邻。该方法还可以包括由处理器将最大超额预订区域的所选数量的组件重新分配给目标区域。

2. 发明授权

US08225262B1 Method of and system for placing clock circuits in an integrated circuit 有权
标题翻译：在集成电路中放置时钟电路的方法和系统
公开(公告)号：US08225262B1
公开(公告)日：2012-07-17
申请号：US12406883
申请日：2009-03-18
申请人： Marvin Tom , Wei Mark Fang , Srinivasan Dasasathyan
发明人： Marvin Tom , Wei Mark Fang , Srinivasan Dasasathyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/62
摘要： A method of placing clock circuits in an integrated circuit is disclosed. The method comprises receiving a circuit design to be implemented in the integrated circuit; identifying portions of the circuit design comprising clock circuits; determining an order of clock circuits to be placed based upon resource requirements of the clock circuits; and placing the portions of the circuit design comprising clock circuits in sites of the integrated circuit. A system for placing clock circuits in an integrated circuit is also disclosed.
摘要翻译：公开了一种在集成电路中放置时钟电路的方法。该方法包括接收要在集成电路中实现的电路设计; 识别包括时钟电路的电路设计的部分; 基于时钟电路的资源需求确定要放置的时钟电路的顺序; 以及将包括时钟电路的电路设计的部分放置在集成电路的位置。还公开了一种用于将集成电路中的时钟电路放置的系统。

3. 发明授权

US08230377B1 Control set constraint driven force directed analytical placer for programmable integrated circuits 有权
标题翻译：用于可编程集成电路的控制集约束驱动力定向分析仪
公开(公告)号：US08230377B1
公开(公告)日：2012-07-24
申请号：US12429991
申请日：2009-04-24
申请人： Wei Mark Fang , Srinivasan Dasasathyan
发明人： Wei Mark Fang , Srinivasan Dasasathyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer-implemented method of globally placing a circuit design on a programmable integrated circuit (IC) includes dividing, by a placement system, the programmable IC into a grid comprising a plurality of cells, assigning each component of a selected component type of the circuit design to one of a plurality of control set groups according to a control set of the component, and calculating a force including a control set force that depends upon overlap of control sets within the plurality of cells. The method further can include applying the force to at least one selected component of the circuit design and assigning components of the circuit design to locations on the programmable IC by solving a set of linear equations that depend upon application of the force to the at least one selected component to create a global placement. The circuit design including the global placement can be output.
摘要翻译：将电路设计全局放置在可编程集成电路（IC）上的计算机实现的方法包括将布置系统将可编程IC划分成包括多个单元的网格，分配电路的所选组件类型的每个组件根据组件的控制组设计为多个控制组组中的一组，并且计算包括依赖于多个单元内的控制组的重叠的控制设定力的力。该方法还可以包括将力施加到电路设计的至少一个选定部件，并通过求解一组依赖于将力施加到至少一个的线性方程组来将电路设计的部件分配给可编程IC上的位置选择的组件来创建全局展示位置。可以输出包括全局放置的电路设计。

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