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1. 发明授权

US5655133A Massively multiplexed superscalar Harvard architecture computer 失效
标题翻译：大规模多重超标量哈佛架构电脑
公开(公告)号：US5655133A
公开(公告)日：1997-08-05
申请号：US558921
申请日：1995-11-13
申请人： Wayne P. Dupree , Stephen G. Churchill , Jeffry R. Gallant , Larry A. Root , William J. Bressette , Robert A. Orr, III , Srikala Ramaswamy , Jeffrey A. Lucas , James A. Bleck
发明人： Wayne P. Dupree , Stephen G. Churchill , Jeffry R. Gallant , Larry A. Root , William J. Bressette , Robert A. Orr, III , Srikala Ramaswamy , Jeffrey A. Lucas , James A. Bleck
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38 , G06F15/78
CPC分类号： G06F9/3001 , G06F15/7832 , G06F9/30141 , G06F9/3885
摘要： A massively multiplexed central processing unit ("CPU") which has a plurality of independent computational circuits, a separate internal result bus for transmitting the resultant output from each of these computational circuits, and a plurality of general purpose registers coupled to each of the computational circuits. Each of the general purpose registers have multiplexed input ports which are connected to each of the result buses. Each of the general purpose registers also have an output port which is connected to a multiplexed input port of at least one of the computational circuits. Each of the computational circuits are dedicated to at least one unique mathematical function, and at least one of the computational circuits include at least one logical function. At least one of the computational circuits includes a plurality of concurrently operable mathematical and logical processing circuits, and an output multiplexer for selecting one of the resultant outputs for transmission on its result bus. The CPU also features a very long instruction word which uses a series of assigned bit locations to represent the selections codes for each of the CPU components. These selection codes are directly transmitted to each of the CPU components by a program control circuit. A separate data control circuit is further provided in achieve a Harvard architecture design for the CPU.
摘要翻译：具有多个独立计算电路的大量复用的中央处理单元（“CPU”），用于从这些计算电路中的每一个发送所得到的输出的分离的内部结果总线，以及耦合到每个计算电路的多个通用寄存器电路。每个通用寄存器具有连接到每个结果总线的复用输入端口。每个通用寄存器还具有连接到至少一个计算电路的多路复用输入端口的输出端口。每个计算电路专用于至少一个唯一的数学函数，并且至少一个计算电路包括至少一个逻辑功能。计算电路中的至少一个包括多个同时操作的数学和逻辑处理电路，以及输出多路复用器，用于选择其中一个结果输出以在其结果总线上传输。 CPU还具有非常长的指令字，其使用一系列分配的位位置来表示每个CPU组件的选择代码。这些选择码由程序控制电路直接发送到每个CPU组件。为了实现用于CPU的哈佛架构设计，还提供了单独的数据控制电路。

2. 发明授权

US5555424A Extended Harvard architecture computer memory system with programmable variable address increment 失效
标题翻译：扩展哈佛架构计算机存储系统，可编程可变地址增量
公开(公告)号：US5555424A
公开(公告)日：1996-09-10
申请号：US319453
申请日：1994-10-06
申请人： Edward R. Sederlund , Robert J. Lindesmith , Larry A. Root , Wayne P. Dupree , Lowell V. Thomas
发明人： Edward R. Sederlund , Robert J. Lindesmith , Larry A. Root , Wayne P. Dupree , Lowell V. Thomas
IPC分类号： G06F12/02 , G06F12/06 , G06F15/78 , G06F13/00 , G06F12/00
CPC分类号： G06F15/7842
摘要： An extended Harvard architecture memory system which features an address store for containing an ordered sequence of program memory addresses, and a value store for containing a series of related data value sets. Each of the addresses contained in the address store is associated with a distinct set of instructions, such as a subroutine, that is contained in the program memory. The address store may also contain the address of one or more instruction arguments that are, in turn, contained in the value store or in a separate data memory. Both the address store and the value store are preferably connected to the same data communication path which is used by the data memory of the computer. The value store also includes a logic interface for enabling a plurality of different address increments to be programmably selected.
摘要翻译：扩展的哈佛架构存储器系统，其特征在于包含有序序列的程序存储器地址的地址存储器和用于包含一系列相关数据值集合的值存储器。包含在地址存储器中的每个地址与包含在程序存储器中的一组不同的指令相关联，例如子程序。地址存储还可以包含一个或多个指令参数的地址，这些指令参数又包含在值存储器中或在单独的数据存储器中。地址存储器和值存储器都优选地连接到由计算机的数据存储器使用的相同的数据通信路径。值存储还包括用于使得可编程地选择多个不同地址增量的逻辑接口。

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