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1. 发明授权

US07342409B2 System for testing semiconductor components 有权
标题翻译：半导体元件测试系统
公开(公告)号：US07342409B2
公开(公告)日：2008-03-11
申请号：US11516342
申请日：2006-09-06
申请人： Warren M. Farnworth , Mark Tuttle
发明人： Warren M. Farnworth , Mark Tuttle
IPC分类号： G01R31/26
CPC分类号： G01R31/2886
摘要： A system for testing semiconductor components includes an interconnect, an alignment system for aligning a substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. The system can be utilized with a method that includes the steps of bonding the interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect.
摘要翻译：用于测试半导体部件的系统包括互连，用于将衬底对准互连的对准系统，用于将部件接合到互连的接合系统，以及用于加热组件和用于分离的互连的加热系统。互连包括被配置用于结合到组件上并且然后与组件上的组件触点分离的互连触点。该系统可以利用包括以下步骤的方法：将互连件连接到部件以形成结合的电连接，通过结合的电连接施加测试信号，然后将互连件与部件分离。接合步骤可以使用冶金结合进行，并且分离步骤可以使用在互连或部件上的可焊接润湿和焊接不可润湿的金属层进行。在分离步骤期间，可焊接润湿层被溶解，减少了粘合的电连接的粘合性，并允许部件和互连的分离。

2. 发明授权

US07259581B2 Method for testing semiconductor components 有权
标题翻译：半导体元件测试方法
公开(公告)号：US07259581B2
公开(公告)日：2007-08-21
申请号：US11057500
申请日：2005-02-14
申请人： Warren M. Farnworth , Mark Tuttle
发明人： Warren M. Farnworth , Mark Tuttle
IPC分类号： G01R31/26
CPC分类号： G01R31/2886
摘要： A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. A system includes the interconnect, an alignment system for aligning the substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation.
摘要翻译：用于测试半导体部件的方法包括以下步骤：将互连件连接到部件以形成结合的电连接，通过结合的电连接施加测试信号，然后将该互连件与部件分离。接合步骤可以使用冶金结合进行，并且分离步骤可以使用在互连或部件上的可焊接润湿和焊接不可润湿的金属层进行。在分离步骤期间，可焊接润湿层被溶解，减少了粘合的电连接的粘合性，并允许部件和互连的分离。互连包括被配置用于结合到组件上并且然后与组件上的组件触点分离的互连触点。系统包括互连，用于将衬底对准互连的对准系统，用于将组件粘合到互连的接合系统，以及用于加热组件和用于分离的互连的加热系统。

3. 发明授权

US07304491B2 Interconnect for testing semiconductor components 有权
公开(公告)号：US07304491B2
公开(公告)日：2007-12-04
申请号：US11516328
申请日：2006-09-06
申请人： Warren M. Farnworth , Mark Tuttle
发明人： Warren M. Farnworth , Mark Tuttle
IPC分类号： G01R31/26
CPC分类号： G01R31/2886
摘要： An interconnect for testing semiconductor components includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. The interconnect can be utilized with a method that includes the steps of bonding the interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect.

4. 发明授权

US07271611B2 Method for testing semiconductor components using bonded electrical connections 有权
标题翻译：使用接合电连接测试半导体元件的方法
公开(公告)号：US07271611B2
公开(公告)日：2007-09-18
申请号：US11698678
申请日：2007-01-26
申请人： Warren M. Farnworth , Mark Tuttle
发明人： Warren M. Farnworth , Mark Tuttle
IPC分类号： G01R31/26
CPC分类号： G01R31/2886
摘要： A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. A system includes the interconnect, an alignment system for aligning the substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation.
摘要翻译：用于测试半导体部件的方法包括以下步骤：将互连件连接到部件以形成结合的电连接，通过结合的电连接施加测试信号，然后将该互连件与部件分离。接合步骤可以使用冶金结合进行，并且分离步骤可以使用在互连或部件上的可焊接润湿和焊接不可润湿的金属层进行。在分离步骤期间，可焊接润湿层被溶解，减少了粘合的电连接的粘合性，并允许部件和互连的分离。互连包括被配置用于结合到组件上并且然后与组件上的组件触点分离的互连触点。系统包括互连，用于将衬底对准互连的对准系统，用于将组件粘合到互连的接合系统，以及用于加热组件和用于分离的互连的加热系统。

5. 发明申请

US20130003303A1 MICROELECTRONIC DEVICES WITH IMPROVED HEAT DISSIPATION AND METHODS FOR COOLING MICROELECTRONIC DEVICES 有权
标题翻译：具有改进的散热装置的微电子装置和用于冷却微电子装置的方法
公开(公告)号：US20130003303A1
公开(公告)日：2013-01-03
申请号：US13612337
申请日：2012-09-12
申请人： Joseph T. Lindgren , Warren M. Farnworth , William M. Hiatt , Nishant Sinha
发明人： Joseph T. Lindgren , Warren M. Farnworth , William M. Hiatt , Nishant Sinha
IPC分类号： H05K7/20
CPC分类号： H01L23/367 , H01L23/427 , H01L24/31 , H01L2224/16 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/10158 , H01L2924/19041 , H01L2224/0401
摘要： Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.
摘要翻译：本文公开了具有改善的散热的微电子器件，制造微电子器件的方法以及冷却微电子器件的方法。在一个实施例中，微电子器件包括具有第一表面，与第一表面相对的第二表面的微电子衬底以及至少靠近第一表面的多个有源器件。第二表面具有增加第二表面的表面积的多个传热表面特征。在另一个实施例中，具有散热器和单相或多相热导体的外壳可以邻近第二表面定位以传递来自有源器件的热量。

6. 发明申请

US20120104528A1 WAFER-LEVEL PACKAGED MICROELECTRONIC IMAGERS AND PROCESSES FOR WAFER-LEVEL PACKAGING 有权
标题翻译：水平包装微电子成像器和水平包装的工艺
公开(公告)号：US20120104528A1
公开(公告)日：2012-05-03
申请号：US13349143
申请日：2012-01-12
申请人： Salman Akram , Peter A. Benson , Warren M. Farnworth , William M. Hiatt
发明人： Salman Akram , Peter A. Benson , Warren M. Farnworth , William M. Hiatt
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H04N5/2253 , H01L27/14609 , H01L27/14627 , H01L27/14634 , H01L27/14643 , H01L27/14685 , H01L27/14687 , H01L27/1469 , H01L31/02325 , H01L2224/48091 , H04N5/2254 , H01L2924/00014
摘要： The following disclosure describes several embodiments of (1) methods for wafer-level packaging of microelectronic imagers, (2) methods of forming electrically conductive interconnects in microelectronic imagers, (3) methods for forming optical devices for microelectronic imagers, and (4) microelectronic imagers that have been packaged using wafer-level packaging processes. Wafer-level packaging of microelectronic imagers is expected to significantly enhance the efficiency of manufacturing microelectronic imagers because a plurality of imagers can be packaged simultaneously using highly accurate and efficient processes developed for packaging semiconductor devices. Moreover, wafer-level packaging of microelectronic imagers is expected to enhance the quality and performance of such imagers because the semiconductor fabrication processes can reliably align an optical device with an image sensor and space the optical device apart from the image sensor by a desired distance with a higher degree of precision.
摘要翻译：以下公开内容描述了（1）用于微电子成像器的晶片级封装的方法的几个实施例，（2）在微电子成像器中形成导电互连的方法，（3）用于形成微电子成像器的光学器件的方法，以及（4）微电子使用晶圆级封装工艺封装的成像仪。预期微电子成像器的晶片级封装将显着提高制造微电子成像器的效率，因为可以使用开发用于封装半导体器件的高精度和有效的工艺同时封装多个成像器。此外，微电子成像器的晶片级封装有望提高这种成像器的质量和性能，因为半导体制造工艺可以可靠地将光学器件与图像传感器对准，并将光学器件与图像传感器分开，并将其与图像传感器隔开期望的距离，更高的精度。

7. 发明授权

US08115269B2 Integrated circuit package having reduced interconnects 有权
标题翻译：集成电路封装具有减少的互连
公开(公告)号：US08115269B2
公开(公告)日：2012-02-14
申请号：US12710072
申请日：2010-02-22
申请人： Warren M. Farnworth , Jerry M. Brooks
发明人： Warren M. Farnworth , Jerry M. Brooks
IPC分类号： H01L31/075 , H01L31/105 , H01L31/117
CPC分类号： H01L25/0657 , H01L2224/4824 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.
摘要翻译：一种制造集成电路封装的技术。具体地，堆叠的存储器件具有最小的互连。存储器管芯彼此堆叠并电耦合到衬底。通孔设置在基板和/或存储器管芯中以便于电连接，而不需要在每个接口之间进行复杂的互连技术。线键用于完成电路封装。

8. 发明申请

US20110101514A1 VERTICAL SURFACE MOUNT ASSEMBLY AND METHODS 审中-公开
标题翻译：垂直表面安装组件和方法
公开(公告)号：US20110101514A1
公开(公告)日：2011-05-05
申请号：US13005218
申请日：2011-01-12
申请人： Larry D. Kinsman , Jerry M. Brooks , Warren M. Farnworth , Walter L. Moden , Terry R. Lee
发明人： Larry D. Kinsman , Jerry M. Brooks , Warren M. Farnworth , Walter L. Moden , Terry R. Lee
IPC分类号： H01L23/34
CPC分类号： H05K3/301 , H01L2924/0002 , Y10T29/4913 , H01L2924/00
摘要： A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradeable.
摘要翻译：一种可垂直安装的半导体器件组件，包括半导体器件和用于将半导体器件附着到载体衬底的机构。半导体器件的每个接合焊盘都设置在其单个边缘附近。优选地，半导体器件的至少一部分被暴露。对准装置附接到载体基板。可垂直安装的半导体器件封装上的安装元件与对准装置接合以使半导体器件和对准器件互连。优选地，对准装置将垂直安装的半导体器件封装相对于载体衬底垂直固定。接合焊盘和载体基板上的对应端子之间的距离非常小以减少阻抗。垂直安装的半导体器件封装也可以容易地用户升级。

9. 发明授权

US07833832B2 Method of fabricating semiconductor components with through interconnects 有权
标题翻译：通过互连制造半导体器件的方法
公开(公告)号：US07833832B2
公开(公告)日：2010-11-16
申请号：US12412906
申请日：2009-03-27
申请人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
发明人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
IPC分类号： H01L21/00 , H01L29/06 , H05K1/03
CPC分类号： H01L23/3114 , B33Y70/00 , B81B7/0006 , H01L21/76898 , H01L23/13 , H01L23/481 , H01L24/48 , H01L27/14618 , H01L2224/02372 , H01L2224/0401 , H01L2224/13024 , H01L2224/131 , H01L2224/45015 , H01L2224/45624 , H01L2224/45655 , H01L2224/45664 , H01L2224/4813 , H01L2224/48471 , H01L2224/85045 , H01L2224/85207 , H01L2224/85951 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/181 , Y10T29/49147 , H01L2924/20752 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A method for fabricating a semiconductor component with through interconnects can include the steps of providing a semiconductor substrate with substrate contacts, and forming openings from a backside of the substrate aligned with the substrate contacts. The method can also include the steps of providing an interposer substrate (or alternately a second semiconductor substrate), forming projections on the interposer substrate (or on the second semiconductor substrate), and forming conductive vias in the projections. The method can also include the steps of placing the projections in physical contact with the openings, and placing the conductive vias in electrical contact with the substrate contacts. The method can also include the steps of bonding the conductive vias to the substrate contacts, and forming terminal contacts on the interposer substrate (or alternately on one of the semiconductor substrates) in electrical communication with the conductive vias.
摘要翻译：用于通过互连制造半导体部件的方法可以包括以下步骤：提供具有衬底触点的半导体衬底，以及从与衬底触点对准的衬底的背面形成开口。该方法还可以包括提供插入器衬底（或者替代地第二半导体衬底）的步骤，在插入器衬底（或第二半导体衬底上）上形成突起，并在突起中形成导电通孔。该方法还可以包括以下步骤：将突起放置在与开口物理接触的位置，并且将导电通孔放置在与基板触点电接触的位置。该方法还可以包括以下步骤：将导电通孔接合到基板触点，以及在内导体基板（或者替代地在其中一个半导体基板上）上形成与导电通孔电连通的端子触点。

10. 发明授权

US07829385B2 Taped semiconductor device and method of manufacture 有权
标题翻译：带状半导体器件及其制造方法
公开(公告)号：US07829385B2
公开(公告)日：2010-11-09
申请号：US11492764
申请日：2006-07-26
申请人： Warren M. Farnworth
发明人： Warren M. Farnworth
IPC分类号： H01L21/00 , H01L23/04
CPC分类号： H01L23/4951 , H01L23/3114 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/4824 , H01L2224/85399 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , Y10T29/49121 , Y10T29/49146 , Y10T29/49172 , H01L2224/45015 , H01L2924/207
摘要： Printed tape is used to form a leads on chip (LOC) ball grid array (BGA) semiconductor device. Leads for a plurality of devices may be applied simultaneously. Bond wires, glob top encapsulant, and the ball grid arrays for the devices may be formed in single process steps. A low temperature curing adhesive material may be used to reduce the effects of differential thermal expansion between the tape and surface of the wafer. In another embodiment of the invention, anisotropically conductive adhesive material is used to connect bond pads on a wafer to leads printed on a tape.
摘要翻译：印刷胶带用于形成芯片上的引线（LOC）球栅阵列（BGA）半导体器件。可以同时应用多个装置的引线。键合线，球顶密封剂和用于器件的球栅阵列可以在单个工艺步骤中形成。可以使用低温固化粘合剂材料来降低带和表面之间的差热膨胀的影响。在本发明的另一个实施例中，各向异性导电粘合剂材料用于连接晶片上的接合焊盘以将印刷在带上的引线。

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