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1. 发明授权

US06313651B1 Carrier and system for testing bumped semiconductor components 失效
标题翻译：用于测试碰撞半导体元件的载体和系统
公开(公告)号：US06313651B1
公开(公告)日：2001-11-06
申请号：US09322724
申请日：1999-05-28
申请人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , Salman Akram
发明人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , Salman Akram
IPC分类号： G01R3102
CPC分类号： G01R1/0483 , H01L2224/0401 , H01L2224/05552 , H01L2224/48091 , H01L2224/81385 , H01L2924/01021 , H01L2924/01087 , H01L2924/09701 , H01L2924/10155 , H01L2924/15311 , H01L2924/00014
摘要： A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.
摘要翻译：提供了一种半导体载体和系统，用于测试具有接触凸块的凸起的半导体部件，例如芯片和封装。载体包括基底，互连和力施加机构。互连包括适于电接触接触凸块的接触构件的图案。互连可以包括具有形成为凹陷的接触构件的衬底，或者作为突出部的覆盖有导电层的衬底。或者，互连可以是直接结合到载体的基底的多层带。除了提供电连接之外，接触构件通过使接触构件内的接触凸块自对中来执行对准功能。载体还可以包括配置成将部件与互连对准的对准部件。该系统可以包括载体，插座和诸如与测试电路电连接的老化板的测试装置。

2. 发明授权

US6025728A Semiconductor package with wire bond protective member 失效
标题翻译：半导体封装带引线键合保护元件
公开(公告)号：US6025728A
公开(公告)日：2000-02-15
申请号：US845782
申请日：1997-04-25
申请人： David R. Hembree , Salman Akram , Derek Gochnour , Warren M. Farnworth
发明人： David R. Hembree , Salman Akram , Derek Gochnour , Warren M. Farnworth
IPC分类号： G01R1/04 , G01R31/02
CPC分类号： G01R1/0483 , H01L2224/48091 , H01L2924/01079 , H01L2924/16195
摘要： A package, system and method for testing semiconductor dice are provided. The package include a base for retaining the die, and an interconnect having contact members for establishing temporary electrical connections with the die. Electrical paths are formed between terminal contacts on the base, and the contact members on the interconnect, by wires that are wire bonded to conductors on the base and interconnect. The package includes a protective member for protecting the wires and associated wire bonds during assembly, disassembly and handling of the package. The protective member can be formed as a plate mounted to the base and configured to cover the wires and wire bonds. Alternately the protective member can comprise an encapsulating material such as an epoxy resin or silicone elastomer deposited on the wires and wire bonds and then cured.
摘要翻译：提供了一种用于测试半导体晶片的封装，系统和方法。该封装包括用于保持裸片的基座和具有与模具建立临时电连接的接触构件的互连。通过引线接合到基座上的导体和互连件上的导线，在基座上的端子触头与互连件上的接触部件之间形成电气路径。该包装包括用于在组装，拆卸和处理包装过程中保护电线和相关联的线接合的保护构件。保护构件可以形成为安装到基座并被构造成覆盖电线和引线接合的板。替代地，保护构件可以包括诸如环氧树脂或硅氧烷弹性体的封装材料，其沉积在电线和引线键上，然后固化。

3. 发明授权

US5893726A Semiconductor package with pre-fabricated cover and method of fabrication 失效
标题翻译：具有预制盖的半导体封装和制造方法
公开(公告)号：US5893726A
公开(公告)日：1999-04-13
申请号：US990866
申请日：1997-12-15
申请人： Warren M. Farnworth , David R. Hembree , Derek Gochnour , Salman Akram , John O. Jacobson , James M. Wark , Steven G. Thummel
发明人： Warren M. Farnworth , David R. Hembree , Derek Gochnour , Salman Akram , John O. Jacobson , James M. Wark , Steven G. Thummel
IPC分类号： H01L23/04 , H01L23/10 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/10 , H01L23/04 , H01L2224/16 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/01087 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195
摘要： A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provided through the substrate to permit pressure equalization during formation of the seal. The cover can be prefabricated in an enclosed configuration for attachment directly to the substrate, or in a planar configuration for attachment to a peripheral ridge on the substrate. In either embodiment, the cover is removable to permit defective dice to be replaced or repaired.
摘要翻译：半导体封装包括具有安装在其上的一个或多个裸片的衬底和适于保护并形成用于裸片的密封空间的盖。盖可以用模制塑料或冲压金属预制，并使用固化的密封件附接到基底。还可以通过基底提供孔，以在形成密封期间允许压力平衡。盖可以以封闭构造预制成直接附接到基底，或者以平面构造附接到基底上的外围脊。在任一实施例中，盖可移动以允许更换或修理有缺陷的骰子。

4. 发明授权

US5726075A Method for fabricating microbump interconnect for bare semiconductor dice 失效
标题翻译：用于制造裸半导体晶片的微型块互连的方法
公开(公告)号：US5726075A
公开(公告)日：1998-03-10
申请号：US624991
申请日：1996-03-29
申请人： Warren M. Farnworth , David R. Hembree , Derek Gochnour
发明人： Warren M. Farnworth , David R. Hembree , Derek Gochnour
IPC分类号： H01L21/48 , H01L21/60 , H01L21/28
CPC分类号： H01L24/11 , H01L21/4853 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042
摘要： A method for forming an interconnect for a bare semiconductor is provided. The interconnect includes an insulating film with a pattern of conductors and microbumps adapted to make an electrical connection with contact locations on the die. The insulating film and conductors are mounted to a rigid substrate (e.g., silicon) using an lo elastomeric adhesive. The method includes forming conductive bus bars in electrical communication with the pattern of conductors to provide an electrical path for electroplating the microbumps onto the conductors. Following the electroplating step, the bus bars are severed and separate electrical paths are formed to the conductors. The bus bar can also be used in the completed interconnect to provide a common electrical path to select conductors. The interconnect can be used for testing the die or for providing a permanent electrical connection to the die.
摘要翻译：提供了一种用于形成裸半导体的互连的方法。互连包括绝缘膜，其具有适于与裸片上的接触位置进行电连接的导体和微胶片图案。绝缘膜和导体使用弹性体粘合剂安装到刚性基底（例如硅）上。该方法包括形成与导体图案电连通的导电母线，以提供用于将微胶片电镀到导体上的电路径。在电镀步骤之后，母线被切断，并且与导体形成分开的电路径。母线也可用于完成的互连，以提供选择导体的公共电路。互连可用于测试管芯或提供与管芯的永久电连接。

5. 发明授权

US06544461B1 Test carrier with molded interconnect for testing semiconductor components 失效
标题翻译：带有模拟互连的测试载体，用于测试半导体元件
公开(公告)号：US06544461B1
公开(公告)日：2003-04-08
申请号：US09677555
申请日：2000-10-02
申请人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , John O. Jacobson , James M. Wark , Syed Sajid Ahmad
发明人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , John O. Jacobson , James M. Wark , Syed Sajid Ahmad
IPC分类号： B29C4502
CPC分类号： G01R1/0483
摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects. A gasket may be used to protect the interconnect contacts during the molding step.
摘要翻译：提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。载体包括模制塑料基底，引线框架和互连件。互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。替代实施例的载体包括多个互连件模制或层压的板。另外，夹子构件保持电路板上与组件电连通的组件。可以在模制步骤期间使用垫圈来保护互连触点。

6. 发明授权

US6040702A Carrier and system for testing bumped semiconductor components 失效
标题翻译：用于测试碰撞半导体元件的载体和系统
公开(公告)号：US6040702A
公开(公告)日：2000-03-21
申请号：US888075
申请日：1997-07-03
申请人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , Salman Akram
发明人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , Salman Akram
IPC分类号： G01R31/26 , G01R1/04 , G01R1/073 , G01R31/02 , H01L21/66 , H01L23/12 , H01L23/32 , H01R13/631 , H01R13/642 , H01R33/76
CPC分类号： G01R1/0483 , H01L2224/0401 , H01L2224/05552 , H01L2224/81385 , H01L2924/01021 , H01L2924/01087 , H01L2924/09701
摘要： A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.
摘要翻译：提供了一种半导体载体和系统，用于测试具有接触凸块的凸起的半导体部件，例如芯片和封装。载体包括基底，互连和力施加机构。互连包括适于电接触接触凸块的接触构件的图案。互连可以包括具有形成为凹陷的接触构件的衬底，或者作为突出部的覆盖有导电层的衬底。或者，互连可以是直接结合到载体的基底的多层带。除了提供电连接之外，接触构件通过使接触构件内的接触凸块自对中来执行对准功能。载体还可以包括配置成将部件与互连对准的对准部件。该系统可以包括载体，插座和诸如与测试电路电连接的老化板的测试装置。

7. 发明授权

US06208157B1 Method for testing semiconductor components 有权
标题翻译：半导体元件测试方法
公开(公告)号：US06208157B1
公开(公告)日：2001-03-27
申请号：US09298769
申请日：1999-04-23
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0433 , G01R1/0483
摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.
摘要翻译：提供了一种用于测试半导体部件的系统和方法。该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装在插座上用于容纳组件的载体。载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

8. 发明授权

US07049840B1 Hybrid interconnect and system for testing semiconductor dice 失效
公开(公告)号：US07049840B1
公开(公告)日：2006-05-23
申请号：US09302576
申请日：1999-04-30
申请人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , James M. Wark , Derek Gochnour
发明人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , James M. Wark , Derek Gochnour
IPC分类号： G01R31/02
CPC分类号： G01R1/0466 , G01R1/0735
摘要： An interconnect is provided for making electrical connections with a semiconductor die. The interconnect includes a substrate having integrally formed contact members, configured to electrically contact corresponding contact locations on the die. The interconnect also includes a pattern of conductors formed separately from the substrate, and then bonded to the substrate, in electrical communication with the contact members. The conductors can be mounted to a multi layered tape similar to TAB tape, or alternately bonded directly to the substrate. In addition, each conductor can include an opening aligned with a corresponding contact member, and filled with a conductive material, such as a conductive adhesive or solder. The conductive material electrically connects the contact members and conductors, and provides an expansion joint to allow expansion of the conductors without stressing the contact members. Also provided are a system for testing dice that includes the interconnect, and a system for testing wafers wherein the interconnect is formed as a probe card.

9. 发明授权

US06642730B1 Test carrier with molded interconnect for testing semiconductor components 失效
公开(公告)号：US06642730B1
公开(公告)日：2003-11-04
申请号：US10351767
申请日：2003-01-27
申请人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , John O. Jacobson , James M. Wark , Syed Sajid Ahmad
发明人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , John O. Jacobson , James M. Wark , Syed Sajid Ahmad
IPC分类号： G01R3102
CPC分类号： G01R1/0483
摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects.

10. 发明授权

US06353326B2 Test carrier with molded interconnect for testing semiconductor components 失效
标题翻译：带有模拟互连的测试载体，用于测试半导体元件
公开(公告)号：US06353326B2
公开(公告)日：2002-03-05
申请号：US09143300
申请日：1998-08-28
申请人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , John O. Jacobson , James M. Wark , Syed Sajid Ahmad
发明人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , John O. Jacobson , James M. Wark , Syed Sajid Ahmad
IPC分类号： G01R3102
CPC分类号： G01R1/0483
摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects.
摘要翻译：提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。载体包括模制塑料基底，引线框架和互连件。互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。替代实施例的载体包括多个互连件模制或层压的板。另外，夹子构件保持电路板上与组件电连通的组件。

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