专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08897080B2 Variable rate serial to parallel shift register 有权
标题翻译：可变速率串行到并行移位寄存器
公开(公告)号：US08897080B2
公开(公告)日：2014-11-25
申请号：US13630278
申请日：2012-09-28
申请人： Wanfang Tsai
发明人： Wanfang Tsai
IPC分类号： G11C7/10
CPC分类号： G11C7/10 , G11C7/1036 , G11C7/1087 , G11C2207/107
摘要： A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an (N×m)-wide parallel data bus. Based on information on how of the N m-bit wide data units are to be ignored, the data will be clocked out at a variable rate. When loading data off the serial bus into the latch, upon refresh the current data is loaded into all N units of the latch, with one less latch being loaded at each subsequent clock. When the content of a unit of latch is to be ignored on the parallel bus, that unit is closed at the same time as the preceding unit so that it is left with redundant data.
摘要翻译：提出了可用于固定或可变速率串行到并行数据转换的移位寄存器结构。在1到N转换中，在传输到（N×m）范围的并行数据总线之前，数据从m位串行数据总线接收并被加载到N宽m锁存器中。基于关于N m位宽数据单元如何被忽略的信息，数据将以可变速率被输出。当将数据从串行总线加载到锁存器中时，刷新时，当前数据被加载到锁存器的所有N个单元中，每个随后的时钟加载少一个锁存器。当并行总线上的单元的内容被忽略时，该单元与前一个单元同时关闭，以便留下冗余数据。

2. 发明申请

US20130242655A1 Techniques for Accessing Column Selecting Shift Register with Skipped Entries in Non-Volatile Memories 有权
标题翻译：技术访问列选择移位寄存器与非易失性存储器中跳过的条目
公开(公告)号：US20130242655A1
公开(公告)日：2013-09-19
申请号：US13420961
申请日：2012-03-15
申请人： Wanfang Tsai
发明人： Wanfang Tsai
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C29/848
摘要： Techniques are present for locating an initial physical location in a looping shift register with random skips on each loop. Here the shift register is for accessing columns in a non-volatile memory, where defective columns of the array are skipped. A look-up table provides for the initial skip of each loop, providing the number of skips from preceding loop to provide a physical address is close to the actual physical address. A new structure of shift registers then enables an automatic shift mode within the loop. The new structure has an additional register and logic gates that count how many skipped entry before the current pointer and shift the current pointer accordingly.
摘要翻译：存在用于在循环移位寄存器中定位初始物理位置的技术，其中每个循环上都有随机跳过。这里，移位寄存器用于访问非易失性存储器中的列，其中跳过数组的有缺陷的列。查找表提供每个循环的初始跳过，提供从前一循环跳过的数量，以提供物理地址接近实际物理地址。移位寄存器的一种新结构可以在循环内实现自动移位模式。新结构具有一个额外的寄存器和逻辑门，用于计算当前指针之前跳过的条目数量，并相应地移动当前指针。

3. 发明授权

US09076506B2 Variable rate parallel to serial shift register 有权
标题翻译：与串行移位寄存器并行的可变速率
公开(公告)号：US09076506B2
公开(公告)日：2015-07-07
申请号：US13630163
申请日：2012-09-28
申请人： Wanfang Tsai
发明人： Wanfang Tsai
IPC分类号： G11C7/00 , G11C7/10 , G11C19/00 , G11C16/08 , G11C29/00
CPC分类号： G11C7/1036 , G11C16/08 , G11C19/00 , G11C29/82 , G11C2207/107 , G11C2211/5642
摘要： A shift register structure is presented that can be used in variable rate parallel to serial data conversions. In an N to 1 conversion, data is received from an (N×m)-wide parallel data bus in an N by m wide latch. This data can include m-bit wide units of data are to be ignore and the parallel bus clock will be of variable rate due to this data to be skipped, which is not to be put out on to the serial bus. The data is transferred from the latch to an N unit shift register, each unit holding m-bits. Multiplexing circuitry is included so that at least on unit of the shift can receive data from more than one latch location, thereby reducing the number of units in the shift register that may need to be skipped when the data is transferred out on to an m-bit wide serial bus with the bits to be ignored absent.
摘要翻译：提出了可以以可变速率并行到串行数据转换的方式使用移位寄存器结构。在N到1转换中，以N×m宽的锁存器从（N×m）范围的并行数据总线接收数据。该数据可以包括要忽略的m位宽的数据单元，并且由于要跳过的数据，并行总线时钟将是可变速率的，这不会被输出到串行总线。数据从锁存器传送到N单元移位寄存器，每个单元保持m位。包括多路复用电路，使得至少在移位单元上可以从多于一个锁存位置接收数据，从而减少当数据被传送到m位时可能需要跳过的移位寄存器中的单元数，位宽的串行总线与被忽略的位不存在。

4. 发明申请

US20140092690A1 Variable Rate Parallel to Serial Shift Register 有权
标题翻译：可变速率与串行移位寄存器并行
公开(公告)号：US20140092690A1
公开(公告)日：2014-04-03
申请号：US13630163
申请日：2012-09-28
申请人： Wanfang Tsai
发明人： Wanfang Tsai
IPC分类号： G11C7/10
CPC分类号： G11C7/1036 , G11C16/08 , G11C19/00 , G11C29/82 , G11C2207/107 , G11C2211/5642
摘要： A shift register structure is presented that can be used in variable rate parallel to serial data conversions. In an N to I conversion, data is received from an (N×m)-wide parallel data bus in an N by in wide latch. This data can include m-bit wide units of data are to be ignore and the parallel bus clock will be of variable rate due to this data to be skipped, which is not to be put out on to the serial bus. The data is transferred from the latch to an N unit shift register, each unit holding m-bits. Multiplexing circuitry is included so that at least on unit of the shift can receive data from more than one latch location, thereby reducing the number of units in the shift register that may need to be skipped when the data is transferred out on to an m-bit wide serial bus with the bits to be ignored absent.
摘要翻译：提出了可以以可变速率并行到串行数据转换的方式使用移位寄存器结构。在N到I转换中，在宽锁存器中，N（N×m）范围内的并行数据总线接收数据。该数据可以包括要忽略的m位宽的数据单元，并且由于要跳过的数据，并行总线时钟将是可变速率的，这不会被输出到串行总线。数据从锁存器传送到N单元移位寄存器，每个单元保持m位。包括多路复用电路，使得至少在移位单元上可以从多于一个锁存位置接收数据，从而减少当数据被传送到m位时可能需要跳过的移位寄存器中的单元数，位宽的串行总线与被忽略的位不存在。

5. 发明授权

US08842473B2 Techniques for accessing column selecting shift register with skipped entries in non-volatile memories 有权
标题翻译：用于访问列选择移位寄存器的技术，在非易失性存储器中跳过条目
公开(公告)号：US08842473B2
公开(公告)日：2014-09-23
申请号：US13420961
申请日：2012-03-15
申请人： Wanfang Tsai
发明人： Wanfang Tsai
IPC分类号： G11C7/02 , G11C16/06
CPC分类号： G11C16/06 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C29/848
摘要： Techniques are present for locating an initial physical location in a looping shift register with random skips on each loop. Here the shift register is for accessing columns in a non-volatile memory, where defective columns of the array are skipped. A look-up table provides for the initial skip of each loop, providing the number of skips from preceding loop to provide a physical address is close to the actual physical address. A new structure of shift registers then enables an automatic shift mode within the loop. The new structure has an additional register and logic gates that count how many skipped entry before the current pointer and shift the current pointer accordingly.
摘要翻译：存在用于在循环移位寄存器中定位初始物理位置的技术，其中每个循环上都有随机跳过。这里，移位寄存器用于访问非易失性存储器中的列，其中跳过数组的有缺陷的列。查找表提供每个循环的初始跳过，提供从前一循环跳过的数量，以提供物理地址接近实际物理地址。移位寄存器的一种新结构可以在循环内实现自动移位模式。新结构具有一个额外的寄存器和逻辑门，用于计算当前指针之前跳过的条目数量，并相应地移动当前指针。

6. 发明申请

US20140092692A1 Variable Rate Serial to Parallel Shift Register 有权
标题翻译：可变速率串行到并行移位寄存器
公开(公告)号：US20140092692A1
公开(公告)日：2014-04-03
申请号：US13630278
申请日：2012-09-28
申请人： Wanfang Tsai
发明人： Wanfang Tsai
IPC分类号： G11C7/10
CPC分类号： G11C7/10 , G11C7/1036 , G11C7/1087 , G11C2207/107
摘要： A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an (N×m)-wide parallel data bus. Based on information on how of the N m-bit wide data units are to be ignored, the data will be clocked out at a variable rate. When loading data off the serial bus into the latch, upon refresh the current data is loaded into all N units of the latch, with one less latch being loaded at each subsequent clock. When the content of a unit of latch is to be ignored on the parallel bus, that unit is closed at the same time as the preceding unit so that it is left with redundant data.
摘要翻译：提出了可用于固定或可变速率串行到并行数据转换的移位寄存器结构。在1到N转换中，在传输到（N×m）范围的并行数据总线之前，数据从m位串行数据总线接收并被加载到N宽m锁存器中。基于关于N m位宽数据单元如何被忽略的信息，数据将以可变速率被输出。当将数据从串行总线加载到锁存器中时，刷新时，当前数据被加载到锁存器的所有N个单元中，每个随后的时钟加载少一个锁存器。当并行总线上的单元的内容被忽略时，该单元与前一个单元同时关闭，以便留下冗余数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式