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1. 发明申请

US20050227587A1 In-line wafer surface mapping 有权
标题翻译：在线晶圆表面贴图
公开(公告)号：US20050227587A1
公开(公告)日：2005-10-13
申请号：US10810533
申请日：2004-03-26
申请人： Wan-Cheng Yang
发明人： Wan-Cheng Yang
IPC分类号： B24B1/00 , B24B37/04 , B24B49/12
CPC分类号： B24B37/005 , B24B49/12
摘要： A method and apparatus for the topographical profiling of a raw substrate is carried out during in-line processing of the substrate during which additional films and structures have been formed over the raw substrate surface. The method includes forming a dielectric film over the substrate surface and forming a metal film over the dielectric film. The structure is polished and monitored during various stages of the polishing operation. An interferometer is used to monitor the surface being polished and to distinguish between regions where metal remains and regions in which metal has been removed and the underlying dielectric material exposed. Topographical data, such as a substrate map, is generated by monitoring the time at which the metal film is removed from various spatial locations across the substrate. The substrate map may be generated during polishing, for in-line monitoring.
摘要翻译：在原料基板表面上已经形成附加的膜和结构的基板的在线处理期间，进行原始基板的形貌分析的方法和装置。该方法包括在衬底表面上形成电介质膜并在电介质膜上形成金属膜。在抛光操作的各个阶段，抛光和监测该结构。干涉仪用于监测正在抛光的表面，并区分金属残留的区域和金属已经被去除的区域以及暴露的下层电介质材料。通过监测跨越衬底的各个空间位置去除金属膜的时间来生成衬底图等形貌数据。衬底图可以在抛光期间产生，用于在线监测。

2. 发明授权

US07091053B2 In-line wafer surface mapping 有权
标题翻译：在线晶圆表面贴图
公开(公告)号：US07091053B2
公开(公告)日：2006-08-15
申请号：US10810533
申请日：2004-03-26
申请人： Wan-Cheng Yang
发明人： Wan-Cheng Yang
IPC分类号： H01L21/00 , B24B51/00
CPC分类号： B24B37/005 , B24B49/12
摘要： A method and apparatus for the topographical profiling of a raw substrate is carried out during in-line processing of the substrate during which additional films and structures have been formed over the raw substrate surface. The method includes forming a dielectric film over the substrate surface and forming a metal film over the dielectric film. The structure is polished and monitored during various stages of the polishing operation. An interferometer is used to monitor the surface being polished and to distinguish between regions where metal remains and regions in which metal has been removed and the underlying dielectric material exposed. Topographical data, such as a substrate map, is generated by monitoring the time at which the metal film is removed from various spatial locations across the substrate. The substrate map may be generated during polishing, for in-line monitoring.
摘要翻译：在原料基板表面上已经形成附加的膜和结构的基板的在线处理期间，进行原始基板的形貌分析的方法和装置。该方法包括在衬底表面上形成电介质膜并在电介质膜上形成金属膜。在抛光操作的各个阶段，抛光和监测该结构。干涉仪用于监测正在抛光的表面，并区分金属残留的区域和金属已经被去除的区域以及暴露的下层电介质材料。通过监测跨越衬底的各个空间位置去除金属膜的时间来生成衬底图等形貌数据。衬底图可以在抛光期间产生，用于在线监测。

3. 发明授权

US06953608B2 Solution for FSG induced metal corrosion & metal peeling defects with extra bias liner and smooth RF bias ramp up 有权
标题翻译： FSG引起金属腐蚀和金属剥离缺陷的解决方案，具有额外的偏置衬垫和平滑的RF偏置斜坡上升
公开(公告)号：US06953608B2
公开(公告)日：2005-10-11
申请号：US10421187
申请日：2003-04-23
申请人： Pong-Hsiung Leu , Yu-Min Chang , Fang-Wen Tsai , Jo-Wei Chen , Wan-Cheng Yang , Chyi-Tsong Ni
发明人： Pong-Hsiung Leu , Yu-Min Chang , Fang-Wen Tsai , Jo-Wei Chen , Wan-Cheng Yang , Chyi-Tsong Ni
IPC分类号： C23C16/40 , C23C16/505 , H01L21/316 , H01L21/768 , H05H1/24
CPC分类号： H01L21/02164 , C23C16/401 , C23C16/505 , H01L21/02131 , H01L21/022 , H01L21/02274 , H01L21/31612 , H01L21/31629 , H01L21/76832 , H01L21/76834 , H01L21/76837
摘要： A HDP CVD process for depositing a USG liner followed by a FSG dielectric layer on a metal line pattern is described. The substrate is heated in a chamber with a plasma comprised of Ar and O2. A USG liner is deposited in two steps wherein the first step is without an RF bias and the second step is with a moderate RF bias that does not damage the metal lines or an anti-reflective coating on the metal. The moderate RF bias is critical in forming a sputtering component that redeposits USG to form more uniform sidewalls and better coverage at top corners of metal lines. The USG deposition process has a good gap filling capability and significantly reduces device failure rate by preventing corrosion of metal lines during subsequent thermal process cycles. The method also includes a PECVD deposited FSG layer that is planarized to complete an IMD layer.
摘要翻译：描述了用于在金属线图案上沉积USG衬垫以及FSG介电层的HDP CVD工艺。衬底在具有由Ar和O 2 2组成的等离子体的腔室中加热。 USG衬垫沉积在两个步骤中，其中第一步没有RF偏压，第二步采用不损坏金属线或金属上的抗反射涂层的中等RF偏压。中等的RF偏压对于形成溅射部件至关重要，该溅射部件重新沉积USG以形成更均匀的侧壁并且在金属线的顶角处具有更好的覆盖。 USG沉积工艺具有良好的间隙填充能力，并通过防止后续热处理循环中金属管线的腐蚀而显着降低设备故障率。该方法还包括平坦化以完成IMD层的PECVD沉积的FSG层。

4. 发明授权

US06531415B1 Silicon nitride furnace tube low temperature cycle purge for attenuated particle formation 有权
标题翻译：氮化硅炉管低温循环吹扫用于减弱颗粒形成
公开(公告)号：US06531415B1
公开(公告)日：2003-03-11
申请号：US10060482
申请日：2002-01-30
申请人： Wan-Cheng Yang , Ren-Dou Lee
发明人： Wan-Cheng Yang , Ren-Dou Lee
IPC分类号： H01L2131
CPC分类号： C23C16/4408 , C23C16/345 , H01L21/3185
摘要： A method for forming upon a substrate employed within a microelectronics fabrication a silicon nitride dielectric layer with attenuated defects and inhomogeneities. There is provided one or more substrates. There is then provided a reactor tube which is part of an apparatus suitable for providing various gases at elevated temperatures. There is then purged the reactor tube with an inert gas in a low temperature cycle purge (LTCP) step at a temperature below deposition temperature. There is then placed the substrate(s) within a reactor tube. There is then deposited a silicon nitride dielectric layer upon the substrate(s), employing silane and ammonia gases employing a low pressure chemical vapor deposition (LPCVD) method. There is then purged the reaction tube at a temperature below the deposition temperature, followed by removal of the substrate carrier with attenuated formation of particulates and inhomogeneities within and about the silicon nitride layer and reaction tube.
摘要翻译：一种用于在微电子制造中使用的衬底上形成具有减弱的缺陷和不均匀性的氮化硅介电层的方法。提供一个或多个基底。然后提供反应器管，其是适于在升高的温度下提供各种气体的装置的一部分。然后在低于沉积温度的温度下，在低温循环清洗（LTCP）步骤中用惰性气体吹扫反应器管。然后将基底放置在反应器管内。然后使用采用低压化学气相沉积（LPCVD）方法的硅烷和氨气体在衬底上沉积氮化硅介电层。然后在低于沉积温度的温度下吹扫反应管，随后在氮化硅层和反应管内和周围减少微粒形成和不均匀性去除衬底载体。

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