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    • 8. 发明授权
    • Redundant microprocessor control system using locks and keys
    • 冗余微处理器控制系统使用锁和钥匙
    • US5136704A
    • 1992-08-04
    • US372746
    • 1989-06-28
    • Carl M. DanielsenEzzat A. DabbishLarry C. Puhl
    • Carl M. DanielsenEzzat A. DabbishLarry C. Puhl
    • G06F11/00G06F11/16
    • G06F11/1654G06F11/1641G06F11/1645G06F11/165G06F11/0757
    • A redundant processing system includes a pair of processors, each processor having an error detector, a key generator, and a lock circuit. The error detectors sense the outputs generated by their processors and generate an error signal when defective data is sensed. The key generators develop multi-bit codes of known patterns that are disrupted in response to receipt of an error signal from an error detector. The codes generated by the key generators are supplied to lock circuits which produce the same known multi-bit codes, and which compare their own codes to the codes supplied by the key generators. If a mis-match is detected, it will be due to a disrupted code that resulted from an error signal. Data from the processor associated with the error signal is rejected.
    • 冗余处理系统包括一对处理器,每个处理器具有错误检测器,密钥发生器和锁定电路。 误差检测器感测由其处理器产生的输出,并且当感测到缺陷数据时产生误差信号。 密钥生成器开发出已知模式的多位代码,其响应于错误检测器的错误信号的接收而被中断。 由密钥生成器产生的代码被提供给产生相同的已知多位代码的锁定电路,并将它们自己的代码与密钥发生器提供的代码进行比较。 如果检测到匹配错误,则会由于错误信号导致的代码中断。 与错误信号相关联的处理器的数据被拒绝。
    • 9. 发明授权
    • Method for zero-knowledge authentication of a prover by a verifier providing a user-selectable confidence level and associated application devices
    • 通过提供用户可选择置信水平的验证者和相关联的应用设备对证明者进行零知识认证的方法
    • US07363492B2
    • 2008-04-22
    • US11066639
    • 2005-02-25
    • Douglas A. KuhlmanEzzat A. DabbishLarry C. Puhl
    • Douglas A. KuhlmanEzzat A. DabbishLarry C. Puhl
    • H04L29/00
    • H04L9/3221
    • Authentication is performed to a confidence level (CL) desired by a verifier (220). A prover (210) picks and sends certain same size, square matrices to the verifier (220). A random request bit is sent (234) from the verifier (220) to the prover (210) after the receipt of a certain square matrix. Depending on the request bit, calculations are made (244, 264) by the verifier (220) to determine if the matrices sent from the prover are verifiable. The prover (210) is iteratively authenticated by the verifier (220). Iterations are continued until (320) a count of the iterations (IL) reaches a number sufficient to achieve the desired confidence level (CL). After a delay, more iterations can achieve a higher confidence level by building on previous result of authentication without having to begin at zero. During this delay, the verifier (220) can perform tasks in reliance on the result of authentication. Digital logic can perform the authentication.
    • 验证被执行到由验证器(220)期望的置信水平(CL)。 证明者(210)选择并发送某些相同大小的矩阵到验证者(220)。 在接收到某个正方形矩阵之后,随机请求比特(234)从验证者(220)发送到证明者(210)。 根据请求位,验证器(220)进行计算(244,264),以确定从证明器发送的矩阵是否可验证。 验证器(210)由验证器(220)迭代地认证。 继续迭代直到(320)迭代计数(IL)达到足以达到期望置信水平(CL)的数值。 经过一段延迟,更多的迭代可以通过建立在以前的认证结果上而不必从零开始就可以获得更高的置信水平。 在该延迟期间,验证者(220)可以依赖于认证结果执行任务。 数字逻辑可以执行认证。