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1. 发明授权

US5701022A Semiconductor memory device with trench capacitor 失效
标题翻译：具有沟槽电容器的半导体存储器件
公开(公告)号：US5701022A
公开(公告)日：1997-12-23
申请号：US192188
申请日：1994-02-04
申请人： Walter-Ulrich Kellner , Karl-Heinz Kusters , Wolfgang Muller , Franz-Xaver Stelz
发明人： Walter-Ulrich Kellner , Karl-Heinz Kusters , Wolfgang Muller , Franz-Xaver Stelz
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/10844 , Y10S257/929
摘要： A semiconductor memory configuration in a semiconductor substrate includes bit lines, word lines, and memory cells each including one memory capacitor and one MOS selection transistor having two conducting regions and a gate electrode. Each memory capacitor is connected to one of the conducting regions of the transistor. The other of the conducting regions of the transistor is connected to one of the bit lines, and the gate electrode of the transistor is connected to one of the word lines. An insulating field oxide or buried insulating oxide with substantially vertical sidewalls is provided. A trench lies adjacent to the insulating field oxide or buried insulating oxide and adjacent to one of the conducting regions. The capacitors are each disposed in one trench for each memory cell. A first insulating layer covers the inner trench wall surface. A first electrode of the capacitor is disposed perpendicular to the substrate surface on the first insulating layer completely inside the trench. A second insulating layer is disposed on the first electrode. A second electrode is disposed vertically on the second insulating layer in the trench. A contact is connected between the first electrode of the capacitor and one of the conducting regions of the transistor laterally through an opening formed in the first insulating layer on the inner trench wall surface. Methods for producing the semiconductor memory configuration and a memory matrix having at least four of the memory cells, are also provided.
摘要翻译：半导体衬底中的半导体存储器配置包括位线，字线和存储单元，每个存储单元包括一个存储电容器和一个具有两个导电区域的MOS选择晶体管和一个栅电极。每个存储电容器连接到晶体管的一个导电区域。晶体管的另一个导通区域连接到位线之一，并且晶体管的栅电极连接到一条字线。提供具有基本上垂直侧壁的绝缘场氧化物或掩埋绝缘氧化物。沟槽位于绝缘场氧化物或掩埋绝缘氧化物附近，并且与导电区域之一相邻。电容器各自设置在每个存储单元的一个沟槽中。第一绝缘层覆盖内沟壁表面。电容器的第一电极在沟槽内完全垂直于第一绝缘层上的衬底表面设置。第二绝缘层设置在第一电极上。第二电极垂直地设置在沟槽中的第二绝缘层上。接触件通过形成在内沟槽壁表面上的第一绝缘层中的开口横向连接在电容器的第一电极和晶体管的导电区域中的一个之间。还提供了用于制造半导体存储器配置的方法和具有至少四个存储单元的存储器矩阵。

2. 发明授权

US5843819A Semiconductor memory device with trench capacitor and method for the production thereof 失效
标题翻译：具有沟槽电容器的半导体存储器件及其制造方法
公开(公告)号：US5843819A
公开(公告)日：1998-12-01
申请号：US898514
申请日：1997-07-22
申请人： Walter-Ulrich Kellner , Karl-Heinz Kusters , Wolfgang Muller , Franz-Xaver Stelz
发明人： Walter-Ulrich Kellner , Karl-Heinz Kusters , Wolfgang Muller , Franz-Xaver Stelz
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/10844 , Y10S257/929
摘要： A semiconductor memory configuration in a semiconductor substrate includes bit lines, word lines, and memory cells each including one memory capacitor and one MOS selection transistor having two conducting regions and a gate electrode. Each memory capacitor is connected to one of the conducting regions of the transistor. The other of the conducting regions of the transistor is connected to one of the bit lines, and the gate electrode of the transistor is connected to one of the word lines. An insulating field oxide or buried insulating oxide with substantially vertical sidewalls is provided. A trench lies adjacent to the insulating field oxide or buried insulating oxide and adjacent to one of the conducting regions. The capacitors are each disposed in one trench for each memory cell. A first insulating layer covers the inner trench wall surface. A first electrode of the capacitor is disposed perpendicular to the substrate surface on the first insulating layer completely inside the trench. A second insulating layer is disposed on the first electrode. A second electrode is disposed vertically on the second insulating layer in the trench. A contact is connected between the first electrode of the capacitor and one of the conducting regions of the transistor laterally through an opening formed in the first insulating layer on the inner trench wall surface. Methods for producing the semiconductor memory configuration and a memory matrix having at least four of the memory cells, are also provided.
摘要翻译：半导体衬底中的半导体存储器配置包括位线，字线和存储单元，每个存储单元包括一个存储电容器和一个具有两个导电区域的MOS选择晶体管和一个栅电极。每个存储电容器连接到晶体管的一个导电区域。晶体管的另一个导通区域连接到位线之一，并且晶体管的栅电极连接到一条字线。提供具有基本上垂直侧壁的绝缘场氧化物或掩埋绝缘氧化物。沟槽位于绝缘场氧化物或掩埋绝缘氧化物附近，并且与导电区域之一相邻。电容器各自设置在每个存储单元的一个沟槽中。第一绝缘层覆盖内沟壁表面。电容器的第一电极在沟槽内完全垂直于第一绝缘层上的衬底表面设置。第二绝缘层设置在第一电极上。第二电极垂直地设置在沟槽中的第二绝缘层上。接触件通过形成在内沟槽壁表面上的第一绝缘层中的开口横向连接在电容器的第一电极和晶体管的导电区域中的一个之间。还提供了用于制造半导体存储器配置的方法和具有至少四个存储单元的存储器矩阵。

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