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1. 发明授权

US08239611B2 Relocating data in a memory device 有权
标题翻译：将数据重新定位在存储设备中
公开(公告)号：US08239611B2
公开(公告)日：2012-08-07
申请号：US11966923
申请日：2007-12-28
申请人： Walter Allen , Robert France
发明人： Walter Allen , Robert France
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7205
摘要： Systems and methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.
摘要翻译：提出了可以促进与存储器相关联的数据的更优化重定位的系统和方法。除了存储器控制器组件之外，可以采用存储器管理器组件来增加可用的处理资源，以便更好地执行更高级别的功能。可以将较高级别的功能委派给内存管理器组件，以允许在内存控制器组件资源上减少或无负载地执行这些更高级别的操作。可以采用单总线或多总线架构来进一步优化数据重定位操作。第一总线可以用于数据访问操作，包括读取，写入，擦除，刷新或其组合等，而第二总线可被指定用于更高级操作，包括数据压缩，错误代码校正，损耗均衡或组合其中。

2. 发明授权

US08464021B2 Address caching stored translation 有权
标题翻译：地址缓存存储转换
公开(公告)号：US08464021B2
公开(公告)日：2013-06-11
申请号：US12127919
申请日：2008-05-28
申请人： Walter Allen , Sunil Atri , Robert France
发明人： Walter Allen , Sunil Atri , Robert France
IPC分类号： G06F9/34 , G06F9/26
CPC分类号： G06F12/1027 , G06F12/0246
摘要： Systems and/or methods that facilitate logical block address (LBA) to physical block address (PBA) translations associated with a memory component(s) are presented. The disclosed subject matter employs an optimized block address (BA) component that can facilitate caching the LBA to PBA translations within a memory controller component based in part on a predetermined optimization criteria to facilitate improving the access of data associated with the memory component. The predetermined optimization criteria can relate to a length of time since an LBA has been accessed, a number of times the LBA has been access, a data size of data related to an LBA, and/or other factors. The LBA to PBA translations can be utilized to facilitate accessing the LBA and/or associated data using the cached translation, instead of performing various functions to determine the translation.
摘要翻译：呈现促进逻辑块地址（LBA）到与存储器组件相关联的物理块地址（PBA）转换的系统和/或方法。所公开的主题采用优化的块地址（BA）组件，其可以有助于部分地基于预定的优化标准来促进将LBA缓存到存储器控制器组件内的PBA转换，以便于改进与存储器组件相关联的数据的访问。预定的优化标准可以涉及从LBA被访问以来的时间长度，LBA已经访问的次数，与LBA相关的数据的数据大小和/或其他因素。可以使用LBA到PBA转换来促进使用高速缓存的转换来访问LBA和/或相关联的数据，而不是执行各种功能来确定翻译。

3. 发明申请

US20120271991A1 RELOCATING DATA IN A MEMORY DEVICE 有权
标题翻译：在数据存储器中传送数据
公开(公告)号：US20120271991A1
公开(公告)日：2012-10-25
申请号：US13539688
申请日：2012-07-02
申请人： Walter Allen , Robert France
发明人： Walter Allen , Robert France
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7205
摘要： Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.
摘要翻译：提出了可以促进与存储器相关联的数据的更优化重定位的方法。除了存储器控制器组件之外，可以采用存储器管理器组件来增加可用的处理资源，以便更好地执行更高级别的功能。可以将较高级别的功能委派给内存管理器组件，以允许在内存控制器组件资源上减少或无负载地执行这些更高级别的操作。可以采用单总线或多总线架构来进一步优化数据重定位操作。第一总线可以用于数据访问操作，包括读取，写入，擦除，刷新或其组合等，而第二总线可被指定用于更高级操作，包括数据压缩，错误代码校正，损耗均衡或组合其中。

4. 发明授权

US07949851B2 Translation management of logical block addresses and physical block addresses 有权
标题翻译：逻辑块地址和物理块地址的翻译管理
公开(公告)号：US07949851B2
公开(公告)日：2011-05-24
申请号：US11966919
申请日：2007-12-28
申请人： Walter Allen , Sunil Atri , Robert France
发明人： Walter Allen , Sunil Atri , Robert France
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/1027 , G06F2212/7201
摘要： Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control of performance of calculation functions, table look-up functions, and/or search functions to locate the desired LBA. The memory controller component generates a configuration sequence based in part on predefined optimization criteria to facilitate optimized performance of translations. The memory controller component and/or associated memory component(s) can be configured so that the translation attributes are determined in a desired order using the desired translation function(s) to determine a respective translation attribute based in part on the predefined optimization criteria. The LBA to PBA translations can be performed in parallel by memory components.
摘要翻译：呈现促进与存储器组件相关联的PBA和LBA转换的系统和/或方法。存储器控制器组件有助于确定哪个存储器组件，擦除块，页面和数据块包含存储期望的LBA和/或相关联的数据的PBA。存储器控制器组件便于控制计算功能，表查找功能和/或搜索功能的性能，以定位所需的LBA。内存控制器组件部分地基于预定义的优化标准生成配置顺序，以促进翻译的优化性能。存储器控制器组件和/或相关联的存储器组件可以被配置为使得使用期望的转换功能以期望的顺序确定翻译属性，以部分地基于预定义的优化标准来确定相应的翻译属性。 LBA到PBA转换可以由存储器组件并行执行。

5. 发明申请

US20090161430A1 BIT MAP CONTROL OF ERASE BLOCK DEFECT LIST IN A MEMORY 有权
标题翻译：存储器中擦除块缺陷列表的位图控制
公开(公告)号：US20090161430A1
公开(公告)日：2009-06-25
申请号：US11963286
申请日：2007-12-21
申请人： Walter Allen , Robert France , Sunil Atri
发明人： Walter Allen , Robert France , Sunil Atri
IPC分类号： G11C16/04 , G11C29/00
CPC分类号： G11C29/76
摘要： Systems and methods that facilitate bad block management in a memory device that comprises nonvolatile memory are presented. One or more memory blocks of a memory device are each associated with one or more additional, dedicated bits that facilitate indicating whether the associated memory block is defective. These additional bits, called bad block bits, can be stored in a hardware-based storage mechanism within the memory device. Once a defect is detected in a memory block, at least one of the associated bad block bits can be set to indicate that the memory block is defective. If at least one of the bad block bits associated with a memory block indicates a memory block is defective, access to the memory block can be prevented.
摘要翻译：介绍了在包括非易失性存储器的存储器件中促进坏块管理的系统和方法。存储器设备的一个或多个存储器块都与一个或多个附加的专用位相关联，这些专用位便于指示相关联的存储器块是否有缺陷。称为坏块位的这些附加位可以存储在存储器件内的基于硬件的存储机制中。一旦在存储器块中检测到缺陷，则可以将相关联的坏块位中的至少一个设置为指示存储块有缺陷。如果与存储块相关联的至少一个坏块比特指示存储块是有缺陷的，则可以防止对存储块的访问。

6. 发明授权

US07675776B2 Bit map control of erase block defect list in a memory 有权
标题翻译：存储器中擦除块缺陷列表的位图控制
公开(公告)号：US07675776B2
公开(公告)日：2010-03-09
申请号：US11963286
申请日：2007-12-21
申请人： Walter Allen , Robert France , Sunil Atri
发明人： Walter Allen , Robert France , Sunil Atri
IPC分类号： G11C16/06
CPC分类号： G11C29/76
摘要： Systems and methods that facilitate bad block management in a memory device that comprises nonvolatile memory are presented. One or more memory blocks of a memory device are each associated with one or more additional, dedicated bits that facilitate indicating whether the associated memory block is defective. These additional bits, called bad block bits, can be stored in a hardware-based storage mechanism within the memory device. Once a defect is detected in a memory block, at least one of the associated bad block bits can be set to indicate that the memory block is defective. If at least one of the bad block bits associated with a memory block indicates a memory block is defective, access to the memory block can be prevented.
摘要翻译：介绍了在包括非易失性存储器的存储器件中促进坏块管理的系统和方法。存储器设备的一个或多个存储器块都与一个或多个附加的专用位相关联，这些专用位便于指示相关联的存储器块是否有缺陷。称为坏块位的这些附加位可以存储在存储器件内的基于硬件的存储机制中。一旦在存储器块中检测到缺陷，则可以将相关联的坏块位中的至少一个设置为指示存储器块有缺陷。如果与存储块相关联的至少一个坏块比特指示存储块是有缺陷的，则可以防止对存储块的访问。

7. 发明申请

US20090300318A1 ADDRESS CACHING STORED TRANSLATION 有权
标题翻译：地址缓存存储翻译
公开(公告)号：US20090300318A1
公开(公告)日：2009-12-03
申请号：US12127919
申请日：2008-05-28
申请人： Walter Allen , Sunil Atri , Robert France
发明人： Walter Allen , Sunil Atri , Robert France
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/0246
摘要： Systems and/or methods that facilitate logical block address (LBA) to physical block address (PBA) translations associated with a memory component(s) are presented. The disclosed subject matter employs an optimized block address (BA) component that can facilitate caching the LBA to PBA translations within a memory controller component based in part on a predetermined optimization criteria to facilitate improving the access of data associated with the memory component. The predetermined optimization criteria can relate to a length of time since an LBA has been accessed, a number of times the LBA has been access, a data size of data related to an LBA, and/or other factors. The LBA to PBA translations can be utilized to facilitate accessing the LBA and/or associated data using the cached translation, instead of performing various functions to determine the translation.
摘要翻译：呈现促进逻辑块地址（LBA）到与存储器组件相关联的物理块地址（PBA）转换的系统和/或方法。所公开的主题采用优化的块地址（BA）组件，其可以有助于部分地基于预定的优化标准来促进将LBA缓存到存储器控制器组件内的PBA转换，以便于改进与存储器组件相关联的数据的访问。预定的优化标准可以涉及从LBA被访问以来的时间长度，LBA已经访问的次数，与LBA相关的数据的数据大小和/或其他因素。可以使用LBA到PBA转换来促进使用高速缓存的转换来访问LBA和/或相关联的数据，而不是执行各种功能来确定翻译。

8. 发明申请

US20090172345A1 TRANSLATION MANAGEMENT OF LOGICAL BLOCK ADDRESSES AND PHYSICAL BLOCK ADDRESSES 有权
标题翻译：逻辑块地址和物理地址的翻译管理
公开(公告)号：US20090172345A1
公开(公告)日：2009-07-02
申请号：US11966919
申请日：2007-12-28
申请人： Walter Allen , Sunil Atri , Robert France
发明人： Walter Allen , Sunil Atri , Robert France
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F12/1027 , G06F2212/7201
摘要： Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control of performance of calculation functions, table look-up functions, and/or search functions to locate the desired LBA. The memory controller component generates a configuration sequence based in part on predefined optimization criteria to facilitate optimized performance of translations. The memory controller component and/or associated memory component(s) can be configured so that the translation attributes are determined in a desired order using the desired translation function(s) to determine a respective translation attribute based in part on the predefined optimization criteria. The LBA to PBA translations can be performed in parallel by memory components.
摘要翻译：呈现促进与存储器组件相关联的PBA和LBA转换的系统和/或方法。存储器控制器组件有助于确定哪个存储器组件，擦除块，页面和数据块包含存储期望的LBA和/或相关联的数据的PBA。存储器控制器组件便于控制计算功能，表查找功能和/或搜索功能的性能，以定位所需的LBA。内存控制器组件部分地基于预定义的优化标准生成配置顺序，以促进翻译的优化性能。存储器控制器组件和/或相关联的存储器组件可以被配置为使得使用期望的转换功能以期望的顺序确定翻译属性，以部分地基于预定义的优化标准来确定相应的翻译属性。 LBA到PBA转换可以由存储器组件并行执行。

9. 发明授权

US09734049B2 Relocating data in a memory device 有权
公开(公告)号：US09734049B2
公开(公告)日：2017-08-15
申请号：US13539688
申请日：2012-07-02
申请人： Walter Allen , Robert France
发明人： Walter Allen , Robert France
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7205
摘要： Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.

10. 发明授权

US07979667B2 Memory array search engine 有权
标题翻译：内存阵列搜索引擎
公开(公告)号：US07979667B2
公开(公告)日：2011-07-12
申请号：US11953501
申请日：2007-12-10
申请人： Walter Allen , Robert France
发明人： Walter Allen , Robert France
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F17/30982 , G06F2212/7201
摘要： Systems and/or methods that facilitate a search of a memory component(s) to locate a desired logical block address (LBA) associated with a memory location in a memory component are presented. Searches to locate a desired LBA(s) in a memory component(s) associated with a processor component are offloaded and controlled by the memory component(s). A search component searches pages in the memory array to facilitate locating a page of data associated with an LBA stored in the memory component. The search component can retrieve a portion of a page of data in a block in the memory component to facilitate determining whether the page contains an LBA associated with a command based in part on command information. The search component can search pages in the memory component until a desired page is located or a predetermined number of searches is performed without locating the desired page.
摘要翻译：呈现促进对存储器组件的搜索以定位与存储器组件中的存储器位置相关联的期望逻辑块地址（LBA）的系统和/或方法。搜索在与处理器组件相关联的存储器组件中定位期望的LBA被存储器组件卸载和控制。搜索组件搜索存储器阵列中的页面以便于定位与存储在存储器组件中的LBA相关联的数据页面。搜索组件可以检索存储器组件中的块中的数据页面的一部分，以便部分地基于命令信息来确定页面是否包含与命令相关联的LBA。搜索组件可以搜索存储器组件中的页面，直到找到所需的页面，或者执行预定数量的搜索而不定位所需的页面。

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