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1. 发明授权

US06614285B2 Switched capacitor integrator having very low power and low distortion and noise 失效
标题翻译：开关电容积分器功耗非常低，失真和噪声低
公开(公告)号：US06614285B2
公开(公告)日：2003-09-02
申请号：US09054521
申请日：1998-04-03
申请人： Wai Laing Lee , Dan Kasha , Axel Thomsen
发明人： Wai Laing Lee , Dan Kasha , Axel Thomsen
IPC分类号： G06G7186
CPC分类号： G06G7/1865
摘要： Power available to an integrator circuit is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. In one implementation, increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. The techniques are particularly useful when applied to clocked integrator circuits.
摘要翻译：对集成电路可用的功率进行控制，使得在一个操作阶段期间提供相对较高的功率，例如在期望设备中回转的间隔期间，并且在另一阶段期间提供相对较低的功率。在一个实施方式中，当功率需求预期为高时，无论在特定间隔中是否实际需要高功率，通过切换并联电流镜来提供功率增加。当应用于时钟积分器电路时，这些技术特别有用。

2. 发明授权

US06369745B1 Analog to digital switched capacitor converter using a delta sigma modulator having very low power, distortion and noise 失效
标题翻译：使用具有非常低功率，失真和噪声的Δ-Σ调制器的模数转换电容转换器
公开(公告)号：US06369745B1
公开(公告)日：2002-04-09
申请号：US09054542
申请日：1998-04-03
申请人： Wai Laing Lee , Dan Kasha , Axel Thomsen
发明人： Wai Laing Lee , Dan Kasha , Axel Thomsen
IPC分类号： H03M150
CPC分类号： H03M3/32 , H03M3/374 , H03M3/43 , H03M3/448 , H03M3/452
摘要： Power available to a delta sigma modulator is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. In one implementation, increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. A large step size is selected to reduce power corruption and feedback coefficients are optimized for low power by running at a higher oversampling rate than required by signal to quantization noise requirements.
摘要翻译：控制对ΔΣ调制器的可用功率，使得在一个操作阶段期间提供相对较高的功率，例如在期望设备中回转的间隔期间，并且在另一阶段期间提供相对较低的功率。在一个实施方式中，当功率需求预期为高时，无论在特定间隔中是否实际需要高功率，通过切换并联电流镜来提供功率增加。选择大的步长以减少功率损耗，并且通过以比信号对量化噪声要求所要求的更高的过采样速率运行来为低功率优化反馈系数。

3. 发明授权

US6163286A Digitally driven analog test signal generator 失效
标题翻译：数字驱动模拟测试信号发生器
公开(公告)号：US6163286A
公开(公告)日：2000-12-19
申请号：US89496
申请日：1998-06-02
申请人： Wai Laing Lee , Axel Thomsen , Lei Wang , Dan Kasha
发明人： Wai Laing Lee , Axel Thomsen , Lei Wang , Dan Kasha
IPC分类号： G01R31/28 , H03M3/04 , H03M1/66
CPC分类号： G01R31/2841
摘要： A high performance test signal generator uses a digital to analog converter which converts an N-bit digital signal, such as provided by a computer waveform generator or by a CDROM into an M-bit upsampled digital signal. The M-bit digital signal is applied to an M-bit digital to analog converter to produce an analog output signal. The analog output signal is sampled and fed back across, the discrete time/continuous time interface to the input of the conversion circuit. The test signal generator has very low power consumption yet meets very strict noise and linearity requirements. The test signal generator can be used for testing seismic sensors such as geophones or hydrophones.
摘要翻译：高性能测试信号发生器使用数模转换器，其将诸如由计算机波形发生器或CDROM提供的N位数字信号转换为M位上采样的数字信号。 M位数字信号被施加到M位数模转换器以产生模拟输出信号。模拟输出信号被采样并反馈到离散的时间/连续时间接口到转换电路的输入端。测试信号发生器具有非常低的功耗，但满足非常严格的噪声和线性要求。测试信号发生器可用于测试地震检波器，如地震检波器或水听器。

4. 发明授权

US6130633A Multibit digital to analog converter with feedback across the discrete time/continuous time interface 失效
标题翻译：具有跨越离散时间/连续时间接口的反馈的多位数模转换器
公开(公告)号：US6130633A
公开(公告)日：2000-10-10
申请号：US89489
申请日：1998-06-02
申请人： Wai Laing Lee , Axel Thomsen , Lei Wang , Dan Kasha
发明人： Wai Laing Lee , Axel Thomsen , Lei Wang , Dan Kasha
IPC分类号： H03M3/04 , H03M1/66
CPC分类号： H03M3/50
摘要： A multi-bit digital to analog converter uses both discrete time and continuous time processing to produce an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. In one implementation, the discrete time processing uses an integrator chain of switched capacitor integrators and a switched capacitor low pass filter. The continuous time processor is a 2 pole low pass filter. A finite impulse response filter can precede the discrete time processing. A plurality of analog output sampling arrangements can be selectively applied accommodate a variety of operational conditions.
摘要翻译：多位数模转换器使用离散时间和连续时间处理来产生模拟输出信号。模拟输出信号被采样并通过离散时间/连续时间接口反馈到转换电路的输入端。在一个实现中，离散时间处理使用开关电容器积分器的积分器链和开关电容器低通滤波器。连续时间处理器是2极低通滤波器。有限脉冲响应滤波器可以在离散时间处理之前。可以选择性地应用多个模拟输出采样装置来适应各种操作条件。

5. 发明授权

US6124816A One bit digital to analog converter with relaxed filtering requirements 失效
标题翻译：一个位数字模拟转换器，具有放松的滤波要求
公开(公告)号：US6124816A
公开(公告)日：2000-09-26
申请号：US89497
申请日：1998-06-02
申请人： Wai Laing Lee , Axel Thomsen , Lei Wang , Dan Kasha
发明人： Wai Laing Lee , Axel Thomsen , Lei Wang , Dan Kasha
IPC分类号： H03M3/04 , H03M1/66
CPC分类号： H03M3/508
摘要： A digital to analog converter utilizes two discrete time processing stages, such as switched capacitor integrator circuits, operating at different sampling rates when converting the digital input signal to an analog signal. Use of two different sampling rates relaxes the requirements on antialias filters used in the continuous time processing.
摘要翻译：数模转换器利用两个离散的时间处理级，例如开关电容积分电路，在将数字输入信号转换为模拟信号时，以不同的采样率工作。使用两种不同的采样率可以放松对连续时间处理中使用的抗混叠滤波器的要求。

6. 发明授权

US6124815A Digital to analog converter for correcting for non-linearities in analog devices 失效
标题翻译：用于校正模拟设备中非线性的数模转换器
公开(公告)号：US6124815A
公开(公告)日：2000-09-26
申请号：US89495
申请日：1998-06-02
申请人： Wai Laing Lee , Axel Thomsen , Lei Wang , Dan Kasha
发明人： Wai Laing Lee , Axel Thomsen , Lei Wang , Dan Kasha
IPC分类号： H03M3/04 , H03M1/66
CPC分类号： H03M3/352 , H03M3/50
摘要： A integrated circuit digital to analog converter converts an M-bit digital signal to an analog output signal. The analog output signal can be used to drive external devices such as an off-chip driver. The output of the external device is sampled and fed back across the discrete time/continuous time interface on the chip to the input of the analog to digital converter. Taking the feedback point after the external device ensures relatively high performance for noise and linearity using relatively low performance components, both on and off the chip.
摘要翻译：集成电路数模转换器将M位数字信号转换为模拟输出信号。模拟输出信号可用于驱动外部设备，如片外驱动器。对外部器件的输出进行采样，并将芯片上的离散时间/连续时间接口反馈到模数转换器的输入端。在外部器件之后采取反馈点，使用相对较低性能的器件（芯片上和芯片上），确保噪声和线性度的相对较高的性能。

7. 发明授权

US6124814A Digital to analog converter having improved noise and linearity performance 失效
标题翻译：具有改善的噪声和线性性能的数模转换器
公开(公告)号：US6124814A
公开(公告)日：2000-09-26
申请号：US89490
申请日：1998-06-02
申请人： Wai Laing Lee , Axel Thomsen , Lei Wang , Dan Kasha
发明人： Wai Laing Lee , Axel Thomsen , Lei Wang , Dan Kasha
IPC分类号： H03M3/04 , H03M1/66
CPC分类号： H03M3/368 , H03M3/50
摘要： A digital to analog converter converts an N-bit digital signal into an M-bit digital signal and provides the M-bit digital signal to a conversion circuit which converts the M-bit signal to an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. An interpolation filter is used to increase the apparent sampling rate of the incoming N-bit signal.
摘要翻译：数模转换器将N位数字信号转换为M位数字信号，并将M位数字信号提供给将M位信号转换为模拟输出信号的转换电路。模拟输出信号被采样并通过离散时间/连续时间接口反馈到转换电路的输入端。内插滤波器用于增加输入N位信号的表观采样率。

8. 发明授权

US6121909A One bit digital to analog converter with feedback across the discrete time/continuous time interface 失效
标题翻译：一个位数字到模拟转换器，具有跨越离散时间/连续时间接口的反馈
公开(公告)号：US6121909A
公开(公告)日：2000-09-19
申请号：US89488
申请日：1998-06-02
申请人： Wai Laing Lee , Axel Thomsen , Lei Wang , Dan Kasha
发明人： Wai Laing Lee , Axel Thomsen , Lei Wang , Dan Kasha
IPC分类号： H03M3/02 , H03M1/66
CPC分类号： H03M3/50
摘要： A 1-bit digital to analog converter uses both discrete time and continuous time processing to produce an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. In one implementation, the discrete time processing uses an integrator chain of switched capacitor integrators and a switched capacitor low pass filter. The continuous time processor is a 2 pole low pass filter. A finite impulse response filter can precede the discrete time processing. A plurality of analog output sampling arrangements can be selectively applied accommodate a variety of operational conditions.
摘要翻译： 1位数模转换器使用离散时间和连续时间处理来产生模拟输出信号。模拟输出信号被采样并通过离散时间/连续时间接口反馈到转换电路的输入端。在一个实现中，离散时间处理使用开关电容器积分器的积分器链和开关电容器低通滤波器。连续时间处理器是2极低通滤波器。有限脉冲响应滤波器可以在离散时间处理之前。可以选择性地应用多个模拟输出采样装置来适应各种操作条件。

9. 发明授权

US06653886B1 Power saving amplifier with selectable current levels 失效
标题翻译：省电放大器，具有可选电流
公开(公告)号：US06653886B1
公开(公告)日：2003-11-25
申请号：US09054415
申请日：1998-04-03
申请人： Wai Laing Lee , Dan Kasha , Axel Thomsen
发明人： Wai Laing Lee , Dan Kasha , Axel Thomsen
IPC分类号： H03K1704
CPC分类号： H03F1/301 , H03F1/0261 , H03F2200/331 , H03K17/04106
摘要： Power available to an amplifier is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing could normally occur and relatively low power is provided during another phase. Increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in particular interval. A control circuit provides switching of the current mirrors in a way which minimizes disruption of amplifier operation.
摘要翻译：控制放大器可用的功率，使得在一个操作阶段期间提供相对高的功率，例如在正常发生回转的间隔期间和在另一个相位期间提供相对较低的功率。当功率需求预期为高时，无论是否在特定间隔内实际需要高功率，通过切换并联电流镜来提供功率。控制电路以最小化放大器操作中断的方式提供电流镜的切换。

10. 发明授权

US06249236B1 Low power seismic device interface and system for capturing seismic signals 失效
标题翻译：低功率地震装置接口和捕获地震信号的系统
公开(公告)号：US06249236B1
公开(公告)日：2001-06-19
申请号：US09054544
申请日：1998-04-03
申请人： Wai Laing Lee , Dan Kasha , Axel Thomsen
发明人： Wai Laing Lee , Dan Kasha , Axel Thomsen
IPC分类号： H03M300
CPC分类号： G01V1/245 , H03M3/32 , H03M3/43 , H03M3/448 , H03M3/452
摘要： A front end for capturing seismic signals uses a voltage doubling circuit and an analog to digital converter (ADC) having different power levels available during respective operational phases. Power available the ADC is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. Increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. A large step size is selected for the ADC to reduce power consumption for a delta sigma modulator used in the ADC and feedback coefficients are optimized for low power by running at a higher oversampling rate than required by signal to quantization noise requirements.
摘要翻译：用于捕获地震信号的前端使用在相应的操作阶段期间具有不同功率电平的电压倍增电路和模数转换器（ADC）。功率可用，ADC被控制，使得在一个操作阶段期间提供相对较高的功率，例如在期望设备中回转的间隔期间，并且在另一阶段期间提供相对较低的功率。当功率需求预期为高时，不管是否在特定间隔内实际需要高功率，通过切换并联电流镜来提供功率。 ADC选择了大的步长以减少ADC中使用的ΔΣ调制器的功耗，并且通过以比信号对量化噪声要求所需的更高的过采样速率运行，针对低功率优化了反馈系数。

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