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1. 发明授权

US07215269B2 Delta-sigma analog-to-digital converter suitable for use in a radio receiver channel 失效
公开(公告)号：US07215269B2
公开(公告)日：2007-05-08
申请号：US11249236
申请日：2005-10-12
申请人： Wai L. Lee , Xudong Zhao , Amit Kumar , Jianping Wen , Garry N Link
发明人： Wai L. Lee , Xudong Zhao , Amit Kumar , Jianping Wen , Garry N Link
IPC分类号： H03M3/00
CPC分类号： H03M3/452 , H03H11/04 , H03H17/0664 , H03H2218/04 , H03H2218/10 , H03M3/424 , H03M3/448 , H03M3/454 , H03M3/462
摘要： A radio receiver channel includes an analog front end and a digital signal processing section coupled together by an analog-to-digital converter (ADC) having a delta-sigma modulator coupled to a first digital decimation filter, which is coupled to second digital decimation filter, wherein the first decimation filter includes a source of finite impulse response coefficients coupled so as to provide a plurality of coefficients. The delta-sigma modulator includes a loop filter having a plurality of serially coupled integrators, and a multi-bit quantizer coupled to the loop filter; the multi-bit quantizer including an ADC operable to produce a multi-bit digital output signal, the ADC coupled to a DAC having dual DAC feedback loops, and a dynamic element matching function. In one embodiment, the delta-sigma modulator includes a fifth-order loop filter having five serially coupled integrators with a feedback path from the output to the input of the fifth integrator and a feedback path from the output to the input of the third integrator.

2. 发明申请

US20070080843A1 Delta-sigma analog-to-digital converter suitable for use in a radio receiver channel 失效
标题翻译：适用于无线电接收机通道的Delta-sigma模数转换器
公开(公告)号：US20070080843A1
公开(公告)日：2007-04-12
申请号：US11249236
申请日：2005-10-12
申请人： Wai Lee , Xudong Zhao , Amit Kumar , Jianping Wen , Garry Link
发明人： Wai Lee , Xudong Zhao , Amit Kumar , Jianping Wen , Garry Link
IPC分类号： H03M1/12
CPC分类号： H03M3/452 , H03H11/04 , H03H17/0664 , H03H2218/04 , H03H2218/10 , H03M3/424 , H03M3/448 , H03M3/454 , H03M3/462
摘要： A radio receiver channel includes an analog front end and a digital signal processing section coupled together by an analog-to-digital converter (ADC) having a delta-sigma modulator coupled to a first digital decimation filter, which is coupled to second digital decimation filter, wherein the first decimation filter includes a source of finite impulse response coefficients coupled so as to provide a plurality of coefficients. The delta-sigma modulator includes a loop filter having a plurality of serially coupled integrators, and a multi-bit quantizer coupled to the loop filter; the multi-bit quantizer including an ADC operable to produce a multi-bit digital output signal, the ADC coupled to a DAC having dual DAC feedback loops, and a dynamic element matching function. In one embodiment, the delta-sigma modulator includes a fifth-order loop filter having five serially coupled integrators with a feedback path from the output to the input of the fifth integrator and a feedback path from the output to the input of the third integrator.
摘要翻译：无线电接收机通道包括模拟前端和数字信号处理部分，该数字信号处理部分由具有耦合到第一数字抽取滤波器的Δ-Σ调制器的模数转换器（ADC）耦合在一起，该Δ-Σ调制器耦合到第二数字抽取滤波器，其中所述第一抽取滤波器包括耦合以便提供多个系数的有限脉冲响应系数的源。 Δ-Σ调制器包括具有多个串联耦合的积分器的环路滤波器和耦合到环路滤波器的多位量化器; 多位量化器包括可操作以产生多位数字输出信号的ADC，耦合到具有双DAC反馈回路的DAC的ADC和动态元件匹配功能。在一个实施例中，Δ-Σ调制器包括具有五个串联耦合积分器的五阶环路滤波器，其具有从第五积分器的输出到输入的反馈路径以及从第三积分器的输出到输入的反馈路径。

3. 发明授权

US08526551B2 Multiple-input, on-chip oscilloscope 有权
标题翻译：多路输入，片上示波器
公开(公告)号：US08526551B2
公开(公告)日：2013-09-03
申请号：US12791755
申请日：2010-06-01
申请人： James P. Flynn , Junqi Hua , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , Junqi Hua , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： H03D1/04
CPC分类号： G01R13/0272 , G01R31/2884 , G01R31/3171 , H04L25/03878 , H04L27/01
摘要： An integrated circuit that includes a receive data path is described. The receive data path: equalizes a received analog signal, converts the resulting equalized analog signal to digital data values based on a clock signal, and recovers the clock signal in the digital data values. The integrated circuit also includes an on-chip oscilloscope. The oscilloscope includes: two comparators, a phase rotator that outputs an oscilloscope clock signal whose phase can be varied relative to that of the recovered clock signal, and an offset circuit that outputs a voltage offset. Based on the voltage offset and the oscilloscope clock signal, the comparators output digital values which can be used to determine eye patterns that correspond to the analog signal before and after equalization. The eye patterns can then be correlated with an error rate associated with the received data.
摘要翻译：描述了包括接收数据路径的集成电路。接收数据路径：对接收到的模拟信号进行均衡，基于时钟信号将所得到的均衡模拟信号转换为数字数据值，并恢复数字数据值中的时钟信号。该集成电路还包括片上示波器。示波器包括：两个比较器，一个相位旋转器，输出示波器时钟信号，相位可以相对于恢复的时钟信号的相位变化;以及偏移电路，输出电压偏移。基于电压偏移和示波器时钟信号，比较器输出可用于确定与均衡前后的模拟信号相对应的眼图的数字值。然后眼图可以与与接收的数据相关联的错误率相关联。

4. 发明授权

US08208591B2 Method and apparatus for performing adaptive equalization 有权
标题翻译：用于执行自适应均衡的方法和装置
公开(公告)号：US08208591B2
公开(公告)日：2012-06-26
申请号：US12819629
申请日：2010-06-21
申请人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： H04B1/10
CPC分类号： H04L25/03019 , H04L2025/03617 , H04L2025/03656 , H04L2025/037
摘要： Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.
摘要翻译：描述了用于适配和/或优化接收机的均衡器的系统和技术。可以通过修改一个或多个均衡参数来调整均衡器的行为。在适应和/或优化过程的开始时，系统可以确定一个或多个均衡参数的鲁棒的初始值。然后，系统可以通过迭代地调整一个或多个均衡参数来适应和/或优化均衡器。具体来说，在每个迭代中，系统可以使用接收机的时钟和数据恢复（CDR）电路来确定与一个或多个数据模式相关联的早期和晚期数据转换的数量。接下来，系统可以调整一个或多个均衡参数，使得对于一个或多个数据模式中的每个数据模式，早期数据转换的数量与后期数据转换的数量之间的比率基本上等于期望值。

5. 发明申请

US20110310947A1 METHOD AND APPARATUS FOR PERFORMING ADAPTIVE EQUALIZATION 有权
标题翻译：用于执行自适应均衡的方法和装置
公开(公告)号：US20110310947A1
公开(公告)日：2011-12-22
申请号：US12819629
申请日：2010-06-21
申请人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： H03H7/30
CPC分类号： H04L25/03019 , H04L2025/03617 , H04L2025/03656 , H04L2025/037
摘要： Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.
摘要翻译：描述了用于适配和/或优化接收机的均衡器的系统和技术。可以通过修改一个或多个均衡参数来调整均衡器的行为。在适应和/或优化过程的开始时，系统可以确定一个或多个均衡参数的鲁棒的初始值。然后，系统可以通过迭代地调整一个或多个均衡参数来适应和/或优化均衡器。具体来说，在每个迭代中，系统可以使用接收机的时钟和数据恢复（CDR）电路来确定与一个或多个数据模式相关联的早期和晚期数据转换的数量。接下来，系统可以调整一个或多个均衡参数，使得对于一个或多个数据模式中的每个数据模式，早期数据转换的数量与后期数据转换的数量之间的比率基本上等于期望值。

6. 发明授权

US06784110B2 Method of etching shaped features on a substrate 失效
标题翻译：在基板上蚀刻成形特征的方法
公开(公告)号：US06784110B2
公开(公告)日：2004-08-31
申请号：US10263019
申请日：2002-10-01
申请人： Jianping Wen , Meihua Shen , Hung-Kwei Hu
发明人： Jianping Wen , Meihua Shen , Hung-Kwei Hu
IPC分类号： H01L21302
CPC分类号： H01L21/32137
摘要： In a method of etching a substrate, a substrate is provided in a process zone, the substrate having a pattern of features comprising dielectric covering semiconductor. In a first stage, an energized first etching gas is provided in the process zone, the energized first etching gas having a first selectivity of etching dielectric to semiconductor of at least about 1.8:1, wherein the dielectric is etched preferentially to the semiconductor to etch through the dielectric to at least partially expose the semiconductor. In a second stage, an energized second etching gas is provided in the process zone, the energized second etching gas having a second selectivity of etching dielectric to semiconductor of less than about 1:1.8, wherein the semiconductor is etched preferentially to the dielectric.
摘要翻译：在蚀刻衬底的方法中，在工艺区域中设置衬底，衬底具有包括电介质覆盖半导体的特征图案。在第一阶段中，在处理区域中提供通电的第一蚀刻气体，所激发的第一蚀刻气体具有至少约1.8:1的对半导体的蚀刻电介质的第一选择性，其中电介质优先蚀刻到半导体以蚀刻通过电介质至少部分地暴露半导体。在第二阶段中，在处理区域中提供通电的第二蚀刻气体，所通电的第二蚀刻气体具有小于约1：1.8的蚀刻电介质至半导体的第二选择性，其中半导体优先蚀刻到电介质。

7. 外观设计

USD933416S1 Food processor 有权
公开(公告)号：USD933416S1
公开(公告)日：2021-10-19
申请号：US29766590
申请日：2021-01-15
申请人： Jianping Wen
设计人： Jianping Wen

8. 发明授权

US08589708B2 Reducing power consumption in clock and data recovery systems 有权
标题翻译：降低时钟和数据恢复系统的功耗
公开(公告)号：US08589708B2
公开(公告)日：2013-11-19
申请号：US12797411
申请日：2010-06-09
申请人： James P. Flynn , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： G06F1/32 , G06F1/06
CPC分类号： H03L7/093
摘要： Some embodiments provide a clock and data recovery (CDR) system to recover clock and data information from an analog signal. The CDR system may include an integral path and a proportional path that are part of an integral-proportional control loop. The integral path may be used to track frequency changes in a clock signal that is embedded in the analog signal, while the proportional path may be used to track phase changes in the clock signal that is embedded in the analog signal. The proportional path may be executed at a first clock frequency, while the integral path may be executed at a second clock frequency that is lower than the first clock frequency to reduce the power consumption of the CDR system.
摘要翻译：一些实施例提供了一种从模拟信号中恢复时钟和数据信息的时钟和数据恢复（CDR）系统。 CDR系统可以包括作为积分比例控制回路的一部分的积分路径和比例路径。积分路径可以用于跟踪嵌入在模拟信号中的时钟信号中的频率变化，而比例路径可以用于跟踪嵌入在模拟信号中的时钟信号中的相位变化。比例路径可以以第一时钟频率执行，而积分路径可以在低于第一时钟频率的第二时钟频率下执行，以减少CDR系统的功耗。

9. 发明申请

US20110310942A1 HIGHLY FLEXIBLE FRACTIONAL N FREQUENCY SYNTHESIZER 有权
标题翻译：高灵敏度的零频合成器
公开(公告)号：US20110310942A1
公开(公告)日：2011-12-22
申请号：US12819683
申请日：2010-06-21
申请人： James P. Flynn , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin , Dino A. Toffolon , Jasjeet Singh
发明人： James P. Flynn , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin , Dino A. Toffolon , Jasjeet Singh
IPC分类号： H03L7/00 , H04L7/00 , H04B1/38
CPC分类号： H03L7/183 , H03L7/081
摘要： One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.
摘要翻译：本发明的一个实施例提供了一种用于合成分数频率的锁相环（PLL）。 PLL可以包括1 / N分频器，压控振荡器（VCO），可编程相位混频器和相位检测器。可编程相位混频器可以耦合在VCO的输出端和分频器的输入端之间，其中可编程相位混频器配置成从VCO接收输出时钟信号，并通过改变相位产生频率为f1的第一时钟信号的输出时钟信号。分频器被配置为从可编程相位混合器接收第一时钟信号，并产生频率为f2 = f1 / N的第二时钟信号。相位检测器可以接收参考时钟信号和第二个时钟信号作为输入，并且相位检测器的输出可用于产生VCO的控制电压。

10. 发明授权

US08184757B2 Pattern agnostic on-die scope 有权
标题翻译：图案不可知的在线范围
公开(公告)号：US08184757B2
公开(公告)日：2012-05-22
申请号：US12819660
申请日：2010-06-21
申请人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： H04L7/00
CPC分类号： H04L1/205 , G01R13/0218
摘要： An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can receive the voltage threshold, the scope clock signal, and the input signal, and output a scope bit-stream. The eye-diagram data collection circuitry can detect one or more bit-patterns in the recovered bit-stream, and modify values of one or more scope counters based solely or partly on the scope bit-stream and the recovered bit-stream.
摘要翻译：描述了一个模内范围。在线范围可以包括一个或多个范围限幅器，相位扫描电路，电压扫描电路和眼图数据收集电路。时钟和数据恢复电路可以接收输入信号，并输出恢复的时钟信号和恢复的比特流。相位扫描电路可以接收恢复的时钟信号，并通过向恢复的时钟信号添加相位偏移来输出示波器时钟信号。示波器限幅器可以接收电压阈值，示波器时钟信号和输入信号，并输出示波器位流。眼图数据收集电路可以检测恢复的比特流中的一个或多个比特模式，并且单独或部分地基于范围比特流和恢复的比特流来修改一个或多个范围计数器的值。

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