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1. 发明授权

US06534759B1 Vertical photodetector with improved photocarrier separation and low capacitance 有权
标题翻译：具有改进的光载流子分离和低电容的垂直光电探测器
公开(公告)号：US06534759B1
公开(公告)日：2003-03-18
申请号：US09950121
申请日：2001-09-10
申请人： Waclaw C. Koscielniak , Philipp Lindorfer
发明人： Waclaw C. Koscielniak , Philipp Lindorfer
IPC分类号： H01L3100
CPC分类号： H01L27/14645 , H01L31/101 , H01L31/103 , H01L31/18
摘要： A vertical photodetector for detecting different wavelengths of light. The structure provides doped regions, which are separated by barrier regions. The doped regions detect photons corresponding to different wavelengths of light. Specifically, by detecting the amount of electrical charge collected by diodes positioned in the different doped regions, different wavelengths of light can be detected. The barrier regions inhibit the flow of electrical charges from one doped region into another doped region. The area of the doped regions can be increased, without increasing the capacitance of the diodes which are used to detect the electrical charges generated by light incident of the vertical photodetector.
摘要翻译：用于检测不同波长的光的垂直光电探测器。该结构提供掺杂区域，其被屏障区域分隔开。掺杂区域检测对应于不同波长的光的光子。具体地，通过检测位于不同掺杂区域中的二极管收集的电荷量，可以检测不同波长的光。阻挡区域阻止电荷从一个掺杂区域流入另一个掺杂区域。可以增加掺杂区域的面积，而不增加用于检测由垂直光电检测器入射的光产生的电荷的二极管的电容。

2. 发明授权

US5581110A Integrated circuit with trenches and an oxygen barrier layer 失效
标题翻译：具有沟槽和氧阻隔层的集成电路
公开(公告)号：US5581110A
公开(公告)日：1996-12-03
申请号：US516114
申请日：1995-08-17
申请人： Reda R. Razouk , Kulwant S. Egan , Wipawan Yindeepol , Waclaw C. Koscielniak
发明人： Reda R. Razouk , Kulwant S. Egan , Wipawan Yindeepol , Waclaw C. Koscielniak
IPC分类号： H01L21/3105 , H01L21/334 , H01L21/762 , H01L27/12
CPC分类号： H01L29/66181 , H01L21/3105 , H01L21/76264 , H01L21/76275 , H01L21/76286
摘要： A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.
摘要翻译：公开了具有与半导体衬底的表面相交的壁和衬在壁上的氧化/扩散阻挡层的沟槽。氧化/扩散屏障在沟槽的边缘上延伸，以防止例如沟槽中的应力缺陷和沟槽内的垂直鸟嘴形成。在沟槽内沉积诸如多晶硅的填充材料，随后在沟槽上沉积平坦化层。在施加热量之后，平坦化层流动以在沟槽上形成平坦化层。使用高压磷硅玻璃作平坦化层，平坦化层在低温下适当地流动短时间。

3. 发明授权

US06329698B1 Forming a self-aligned epitaxial base bipolar transistor 有权
标题翻译：形成自对准外延基极双极晶体管
公开(公告)号：US06329698B1
公开(公告)日：2001-12-11
申请号：US09399911
申请日：1999-09-21
申请人： Waclaw C. Koscielniak , Kulwant S. Egan , Jayasimha S. Prasad
发明人： Waclaw C. Koscielniak , Kulwant S. Egan , Jayasimha S. Prasad
IPC分类号： H01K27082
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/732
摘要： An improved method and an apparatus for forming a self-aligned epitaxial base bipolar transistor in a semiconductor material is disclosed. The method of the invention involves forming an intrinsic base region formed by growing an epitaxial semiconductor material over a collector region. A raised sacrificial emitter core is then formed on the intrinsic base region followed by depositing a substantially conformal spacer layer over the sacrificial emitter core. Next, the spacer material is anisotropically etched such that a protective spacer ring is formed about the sacrificial emitter core. An extrinsic base is then formed by implanting dopant into the epitaxial base region wherein the sacrificial emitter core and the spacer ring preserve an emitter region. The spacer ring also serves to self-align the extrinsic base region to the emitter region. The protective sacrificial emitter core and spacer ring are then removed. The self-aligned epitaxial base bipolar transistor is then formed by doping the emitter region.
摘要翻译：公开了一种用于在半导体材料中形成自对准外延基极双极晶体管的改进方法和装置。本发明的方法涉及形成通过在收集器区域上生长外延半导体材料而形成的本征基极区域。然后在本征基极区上形成升高的牺牲发射极核心，然后在牺牲发射极核心上沉积基本上保形的间隔层。接下来，间隔材料被各向异性地蚀刻，使得围绕牺牲发射极芯形成保护性间隔环。然后通过将掺杂剂注入到外延基极区域中形成外部基极，其中牺牲发射极芯和间隔环保留发射极区域。间隔环还用于将外部碱性区域自对准至发射极区域。然后去除保护性牺牲发射极芯和间隔环。然后通过掺杂发射极区域形成自对准外延基极双极晶体管。

4. 发明授权

US5911109A Method of forming an integrated circuit including filling and planarizing a trench having an oxygen barrier layer 失效
标题翻译：形成集成电路的方法，包括填充和平坦化具有氧阻隔层的沟槽
公开(公告)号：US5911109A
公开(公告)日：1999-06-08
申请号：US800012
申请日：1997-02-13
申请人： Reda R. Razouk , Kulwant S. Egan , Wipawan Yindeepol , Waclaw C. Koscielniak
发明人： Reda R. Razouk , Kulwant S. Egan , Wipawan Yindeepol , Waclaw C. Koscielniak
IPC分类号： H01L21/3105 , H01L21/334 , H01L21/762 , H01L21/62
CPC分类号： H01L29/66181 , H01L21/3105 , H01L21/76264 , H01L21/76275 , H01L21/76286
摘要： A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.
摘要翻译：公开了具有与半导体衬底的表面相交的壁和衬在壁上的氧化/扩散阻挡层的沟槽。氧化/扩散屏障在沟槽的边缘上延伸，以防止例如沟槽中的应力缺陷和沟槽内的垂直鸟嘴形成。在沟槽内沉积诸如多晶硅的填充材料，随后在沟槽上沉积平坦化层。在施加热量之后，平坦化层流动以在沟槽上形成平坦化层。使用高压磷硅玻璃作平坦化层，平坦化层在低温下适当地流动短时间。

5. 发明授权

US06795231B1 Photonic crystals using a semiconductor-based fabrication process 有权
标题翻译：使用基于半导体的制造工艺的光子晶体
公开(公告)号：US06795231B1
公开(公告)日：2004-09-21
申请号：US10634179
申请日：2003-08-05
申请人： Waclaw C. Koscielniak
发明人： Waclaw C. Koscielniak
IPC分类号： G02F100
CPC分类号： G02B6/1225 , B82Y20/00
摘要： A photonic crystal is formed on a semiconductor substrate using a semiconductor-based fabrication process by forming a number of alternating layers of material that have different dielectric constants. The layers of material are then etched to form a number of spaced-apart stacks of alternating layers of material. An interstack material is then formed between the stacks.
摘要翻译：使用基于半导体的制造工艺在半导体衬底上形成光子晶体，通过形成具有不同介电常数的材料的多个交替层。然后蚀刻材料层以形成交替的材料层的多个间隔开的堆叠。然后在堆叠之间形成层间材料。

6. 发明授权

US06777293B1 DMOS transistor structure with gate electrode trench for high density integration and method of fabricating the structure 有权
标题翻译：具有用于高密度积分的栅电极沟槽的DMOS晶体管结构和制造该结构的方法
公开(公告)号：US06777293B1
公开(公告)日：2004-08-17
申请号：US10726230
申请日：2003-12-01
申请人： Waclaw C. Koscielniak
发明人： Waclaw C. Koscielniak
IPC分类号： H01L21336
CPC分类号： H01L29/4236 , H01L29/42368 , H01L29/7835
摘要： A double diffused MOS (DMOS) transistor structure is provided that uses a trench trough suitable for high-density integration with mixed signal analog and digital circuit applications. The DMOS device can be added to any advanced CMOS process-using shallow trench isolation by adding additional process steps for trench trough formation, a trench implant and a P-body implant. The trench trough and trench implant provide a novel method of forming a drain extension for a high-voltage DMOS device.
摘要翻译：提供了双扩散MOS（DMOS）晶体管结构，其使用适合于与混合信号模拟和数字电路应用的高密度集成的沟槽槽。 DMOS器件可以添加到任何先进的CMOS工艺中 - 通过为沟槽形成添加额外的工艺步骤，沟槽注入和P体植入，使用浅沟槽隔离。沟槽槽和沟槽植入提供了形成用于高压DMOS器件的漏极扩展的新颖方法。

7. 发明授权

US6020246A Forming a self-aligned epitaxial base bipolar transistor 失效
标题翻译：形成自对准外延基极双极晶体管
公开(公告)号：US6020246A
公开(公告)日：2000-02-01
申请号：US42430
申请日：1998-03-13
申请人： Waclaw C. Koscielniak , Kulwant S. Egan , Jayasimha S. Prasad
发明人： Waclaw C. Koscielniak , Kulwant S. Egan , Jayasimha S. Prasad
IPC分类号： H01L21/331 , H01L29/10 , H01L29/732
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/732
摘要： An improved method and an apparatus for forming a self-aligned epitaxial base bipolar transistor in a semiconductor material is disclosed. The method of the invention involves forming an intrinsic base region formed by growing an epitaxial semiconductor material over a collector region. A raised sacrificial emitter core is then formed on the intrinsic base region followed by depositing a substantially conformal spacer layer over the sacrificial emitter core. Next, the spacer material is anisotropically etched such that a protective spacer ring is formed about the sacrificial emitter core. An extrinsic base is then formed by implanting dopant into the epitaxial base region wherein the sacrificial emitter core and the spacer ring preserve an emitter region. The spacer ring also serves to self-align the extrinsic base region to the emitter region. The protective sacrificial emitter core and spacer ring are then removed. The self-aligned epitaxial base bipolar transistor is then formed by doping the emitter region.
摘要翻译：公开了一种用于在半导体材料中形成自对准外延基极双极晶体管的改进方法和装置。本发明的方法涉及形成通过在收集器区域上生长外延半导体材料而形成的本征基极区域。然后在本征基极区上形成升高的牺牲发射极核心，然后在牺牲发射极核心上沉积基本上保形的间隔层。接下来，间隔材料被各向异性地蚀刻，使得围绕牺牲发射极芯形成保护性间隔环。然后通过将掺杂剂注入到外延基极区域中形成外部基极，其中牺牲发射极芯和间隔环保留发射极区域。间隔环还用于将外部碱性区域自对准至发射极区域。然后去除保护性牺牲发射极芯和间隔环。然后通过掺杂发射极区域形成自对准外延基极双极晶体管。

8. 发明授权

US06713814B1 DMOS transistor structure with gate electrode trench for high density integration and method of fabricating the structure 有权
标题翻译：具有用于高密度积分的栅电极沟槽的DMOS晶体管结构和制造该结构的方法
公开(公告)号：US06713814B1
公开(公告)日：2004-03-30
申请号：US10212392
申请日：2002-08-05
申请人： Waclaw C. Koscielniak
发明人： Waclaw C. Koscielniak
IPC分类号： H01L2976
CPC分类号： H01L29/4236 , H01L29/42368 , H01L29/7835
摘要： A double diffused MOS (DMOS) transistor structure is provided that uses a trench trough suitable for high-density integration with mixed signal analog and digital circuit applications. The DMOS device can be added to any advanced CMOS process using shallow trench isolation by adding additional process steps for trench trough formation, a trench implant and a P-body implant. The trench trough and trench implant provide a novel method of forming a drain extension for a high-voltage DMOS device.
摘要翻译：提供了双扩散MOS（DMOS）晶体管结构，其使用适合于与混合信号模拟和数字电路应用的高密度集成的沟槽槽。 DMOS器件可以添加到使用浅沟槽隔离的任何高级CMOS工艺中，为槽槽形成，沟槽植入和P体植入添加额外的工艺步骤。沟槽槽和沟槽植入提供了形成用于高压DMOS器件的漏极扩展的新颖方法。

9. 发明授权

US06633427B1 Method of forming photonic crystals using a semiconductor-based fabrication process 有权
标题翻译：使用基于半导体的制造工艺形成光子晶体的方法
公开(公告)号：US06633427B1
公开(公告)日：2003-10-14
申请号：US09929661
申请日：2001-08-14
申请人： Waclaw C. Koscielniak
发明人： Waclaw C. Koscielniak
IPC分类号： G02F100
CPC分类号： G02B6/1225 , B82Y20/00
摘要： A photonic crystal is formed on a semiconductor substrate using a semiconductor-based fabrication process by forming a number of alternating layers of material that have different dielectric constants. The layers of material are then etched to form a number of spaced-apart stacks of alternating layers of material. An interstack material is then formed between the stacks.
摘要翻译：使用基于半导体的制造工艺在半导体衬底上形成光子晶体，通过形成具有不同介电常数的材料的多个交替层。然后蚀刻材料层以形成交替的材料层的多个间隔开的堆叠。然后在堆栈之间形成堆叠间材料

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