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1. 发明申请

US20070126032A1 FIN FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING FIN FIELD EFFECT TRANSISTOR 审中-公开
标题翻译： FIN场效应晶体管和制造Fin场效应晶体管的方法
公开(公告)号：US20070126032A1
公开(公告)日：2007-06-07
申请号：US11673767
申请日：2007-02-12
申请人： WEN-SHIANG LIAO , Wei-Tsun Shiau , Kuan-Yang Liao
发明人： WEN-SHIANG LIAO , Wei-Tsun Shiau , Kuan-Yang Liao
IPC分类号： H01L29/76
CPC分类号： H01L29/66795 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66507 , H01L29/785
摘要： The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.
摘要翻译：本发明涉及一种制造包括完全硅化栅电极的鳍式场效应晶体管的方法。该方法适用于包括翅片结构，跨骑栅极，源极/漏极区域和形成在其上的电介质层的衬底，其中跨越栅极跨过鳍状结构，源极/漏极区域位于通过跨门和电介质层暴露的翅片结构覆盖基板。该方法包括以下步骤：执行平坦化处理以去除电介质层和第一自对准硅化物层的一部分，直到暴露了跨越栅极的表面，并执行自对准硅化处理以将跨门转换成完全硅化的栅电极。

2. 发明申请

US20060172476A1 Fin field effect transistor and method for manufacturing fin field effect transistor 有权
标题翻译： Fin场效应晶体管及制造鳍式场效应晶体管的方法
公开(公告)号：US20060172476A1
公开(公告)日：2006-08-03
申请号：US11049819
申请日：2005-02-02
申请人： Wen-Shiang Liao , Wei-Tsun Shiau , Kuan-Yang Liao
发明人： Wen-Shiang Liao , Wei-Tsun Shiau , Kuan-Yang Liao
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242
CPC分类号： H01L29/66795 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66507 , H01L29/785
摘要： The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.
摘要翻译：本发明涉及一种制造包括完全硅化栅电极的鳍式场效应晶体管的方法。该方法适用于包括翅片结构，跨骑栅极，源极/漏极区域和形成在其上的电介质层的衬底，其中跨越栅极跨过鳍状结构，源极/漏极区域位于通过跨门和电介质层暴露的翅片结构覆盖基板。该方法包括以下步骤：执行平坦化处理以去除电介质层和第一自对准硅化物层的一部分，直到暴露了跨越栅极的表面，并执行自对准硅化处理以将跨门转换成完全硅化的栅电极。

3. 发明授权

US07319063B2 Fin field effect transistor and method for manufacturing fin field effect transistor 有权
标题翻译： Fin场效应晶体管及制造鳍式场效应晶体管的方法
公开(公告)号：US07319063B2
公开(公告)日：2008-01-15
申请号：US11049819
申请日：2005-02-02
申请人： Wen-Shiang Liao , Wei-Tsun Shiau , Kuan-Yang Liao
发明人： Wen-Shiang Liao , Wei-Tsun Shiau , Kuan-Yang Liao
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/66507 , H01L29/785
摘要： The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.
摘要翻译：本发明涉及一种制造包括完全硅化栅电极的鳍式场效应晶体管的方法。该方法适用于包括翅片结构，跨骑栅极，源极/漏极区域和形成在其上的电介质层的衬底，其中跨越栅极跨过鳍状结构，源极/漏极区域位于通过跨门和电介质层暴露的翅片结构覆盖基板。该方法包括以下步骤：执行平坦化处理以去除电介质层和第一自对准硅化物层的一部分，直到暴露了跨越栅极的表面，并执行自对准硅化处理以将跨门转换成完全硅化的栅电极。

4. 发明授权

US06853031B2 Structure of a trapezoid-triple-gate FET 有权
标题翻译：梯形三栅极FET的结构
公开(公告)号：US06853031B2
公开(公告)日：2005-02-08
申请号：US10417167
申请日：2003-04-17
申请人： Wen-Shiang Liao , Jiunn-Ren Hwang , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Jiunn-Ren Hwang , Wei-Tsun Shiau
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66787 , H01L29/0657 , H01L29/1037 , H01L29/42376
摘要： A structure of a Trapezoid-Triple-Gate Field Effect Transistor (FET) includes a plurality of trapezoid pillars being transversely formed on an crystalline substrate or Silicon-On-Insulator (SOI) wafer. The trapezoid pillars can juxtapose with both ends connected each other. Each trapezoid pillar has a source, a channel region, and a drain aligned in longitudinal direction and a gate latitudinally superposes the channel region of the trapezoid pillar. The triple gate field effect transistor comprises a dielectric layer formed between the channel region and the conductive gate structure.
摘要翻译：梯形三栅场效应晶体管（FET）的结构包括在晶体衬底或绝缘体上硅晶片上横向形成的多个梯形柱。梯形柱可以并置，两端相互连接。每个梯形柱具有在纵向方向上排列的源极，沟道区和漏极，栅极横向叠加梯形柱的沟道区域。三栅场效应晶体管包括形成在沟道区和导电栅结构之间的电介质层。

5. 发明授权

US07423321B2 Double gate MOSFET device 有权
标题翻译：双栅MOSFET器件
公开(公告)号：US07423321B2
公开(公告)日：2008-09-09
申请号：US10976278
申请日：2004-10-29
申请人： Wen-Shiang Liao , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Wei-Tsun Shiau
IPC分类号： H01L27/01
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66795 , H01L29/66803
摘要： A method of fabricating a double gate MOSFET device is provided. The present invention overetches a silicon layer overlying a buried oxide layer using a hard mask of cap oxide on the silicon layer as an etching mask. As a result, source, drain and channel regions are formed extending from the buried oxide layer, and a pair of recesses are formed under the channel regions in the buried oxide layer. The channel is a fin structure with a top surface and two opposing parallelly sidewalls. The bottom recess is formed under each opposing sidewall of the fin structure. A conductive gate layer is formed straddling the fin structures. The topography of the conductive gate layer significantly deviates from the conventional plainer profile due to the bottom recess structures under the channel regions, and a more uniformly distributed doped conductive gate layer can be obtained. Hence, the depletion effect of the conductive polysilicon gate while operating the device can be suppressed and the device drive-on currents can be further enhanced.
摘要翻译：提供一种制造双栅极MOSFET器件的方法。本发明使用硅层上的氧化碳膜的硬掩模作为蚀刻掩模来蚀刻覆盖掩埋氧化物层的硅层。结果，从掩埋氧化物层形成源极，漏极和沟道区，并且在掩埋氧化物层的沟道区的下方形成一对凹部。通道是具有顶表面和两个相对的平行侧壁的翅片结构。底部凹部形成在翅片结构的每个相对侧壁下方。导电栅极层跨越翅片结构形成。导电栅极层的形貌由于在沟道区下面的底部凹陷结构而显着地偏离常规的平滑轮廓，并且可以获得更均匀分布的掺杂的导电栅极层。因此，可以抑制在操作器件时导电多晶硅栅极的耗尽效应，并且可以进一步提高器件驱动电流。

6. 发明授权

US06855588B1 Method of fabricating a double gate MOSFET device 有权
标题翻译：制造双栅极MOSFET器件的方法
公开(公告)号：US06855588B1
公开(公告)日：2005-02-15
申请号：US10679381
申请日：2003-10-07
申请人： Wen-Shiang Liao , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Wei-Tsun Shiau
IPC分类号： H01L21/336 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66795 , H01L29/66803
摘要： A method of fabricating a double gate MOSFET device is provided. The present invention overetches a silicon layer overlying a buried oxide layer using a hard mask of cap oxide on the silicon layer as an etching mask. As a result, source, drain and channel regions are formed extending from the buried oxide layer, and a pair of recesses are formed under the channel regions in the buried oxide layer. The channel is a fin structure with a top surface and two opposing parallelly sidewalls. The bottom recess is formed under each opposing sidewall of the fin structure. A conductive gate layer is formed straddling the fin structures. The topography of the conductive gate layer significantly deviates from the conventional plainer profile due to the bottom recess structures under the channel regions, and a more uniformly distributed doped conductive gate layer can be obtained. Hence, the depletion effect of the conductive polysilicon gate while operating the device can be suppressed and the device drive-on currents can be further enhanced.
摘要翻译：提供一种制造双栅极MOSFET器件的方法。本发明使用硅层上的氧化碳膜的硬掩模作为蚀刻掩模来蚀刻覆盖掩埋氧化物层的硅层。结果，从掩埋氧化物层形成源极，漏极和沟道区，并且在掩埋氧化物层的沟道区的下方形成一对凹部。通道是具有顶表面和两个相对的平行侧壁的翅片结构。底部凹部形成在翅片结构的每个相对侧壁下方。导电栅极层跨越翅片结构形成。导电栅极层的形貌由于在沟道区下面的底部凹陷结构而显着地偏离常规的平滑轮廓，并且可以获得更均匀分布的掺杂的导电栅极层。因此，可以抑制在操作器件时导电多晶硅栅极的耗尽效应，并且可以进一步提高器件驱动电流。

7. 发明授权

US07326617B2 Method of fabricating a three-dimensional multi-gate device 有权
标题翻译：制造三维多栅极器件的方法
公开(公告)号：US07326617B2
公开(公告)日：2008-02-05
申请号：US11161950
申请日：2005-08-23
申请人： Wen-Shiang Liao , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Wei-Tsun Shiau
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L29/66795 , H01L29/785
摘要： A method for fabricating a three-dimensional multi-gate device includes steps of providing a semiconductor substrate and forming a silicon fin on the semiconductor substrate, the silicon fin having a top surface and two side surfaces; forming a gate structure on the silicon fin, the gate structure partially covering the top surface and the two side surfaces of the silicon fin, and forming a spacer structure on both sides of the gate structure; forming two doped regions in the silicon fin under both sides of the gate structure; and forming a stress-adjusting layer covering the gate structure.
摘要翻译：一种制造三维多栅极器件的方法包括以下步骤：在半导体衬底上提供半导体衬底和形成硅鳍片，所述硅片具有顶表面和两个侧表面; 在所述硅片上形成栅极结构，所述栅极结构部分地覆盖所述硅片的顶表面和所述两个侧表面，并且在所述栅极结构的两侧上形成间隔结构; 在栅极结构的两侧在硅片中形成两个掺杂区域; 以及形成覆盖所述栅极结构的应力调整层。

8. 发明授权

US07256464B2 Metal oxide semiconductor transistor and fabrication method thereof 有权
标题翻译：金属氧化物半导体晶体管及其制造方法
公开(公告)号：US07256464B2
公开(公告)日：2007-08-14
申请号：US11162080
申请日：2005-08-29
申请人： Wen-Shiang Liao , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Wei-Tsun Shiau
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/823418 , H01L21/823814 , H01L29/66636 , H01L29/7834
摘要： A metal oxide semiconductor transistor comprising a first doping type substrate, an isolation layer, a plurality of gates, a masking layer, a gate oxide layer, a plurality of second doping type source/drain regions and spacers. The first doping type substrate has a plurality of trenches patterning out a plurality of first doping type strips. The isolation layer is disposed within the trenches. The gates is disposed over the first doping type strips and oriented in a direction perpendicular to the first doping type strips. The masking layer is disposed over the first doping type substrate. The gate oxide layer is disposed between the sidewall of the first doping type strips and the gate. The second doping type source/drain regions are disposed in the first doping type strip on each side of the gate. The spacers are disposed on the sidewalls of the gates and the first doping type strips.
摘要翻译：一种金属氧化物半导体晶体管，包括第一掺杂型衬底，隔离层，多个栅极，掩模层，栅极氧化物层，多个第二掺杂型源极/漏极区域和间隔物。第一掺杂型衬底具有图案化多个第一掺杂型条带的多个沟槽。隔离层设置在沟槽内。栅极设置在第一掺杂型条带之上并且在垂直于第一掺杂型条带的方向上取向。掩模层设置在第一掺杂型衬底上。栅极氧化物层设置在第一掺杂型条带的侧壁和栅极之间。第二掺杂型源极/漏极区域设置在栅极的每一侧上的第一掺杂型条带中。间隔物设置在栅极和第一掺杂型条带的侧壁上。

9. 发明申请

US20070164325A1 THREE-DIMENSIONAL MULTI-GATE DEVICE AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：三维多门装置及其制作方法
公开(公告)号：US20070164325A1
公开(公告)日：2007-07-19
申请号：US11693739
申请日：2007-03-30
申请人： Wen-Shiang Liao , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Wei-Tsun Shiau
IPC分类号： H01L29/80
CPC分类号： H01L29/7843 , H01L29/66795 , H01L29/785
摘要： A three-dimensional multi-gate device has a silicon fin, a gate structure, and a stress-adjusting layer. The gate structure contacts with three surface of the silicon fin to form a three-dimensional gate structure. The stress-adjusting layer is disposed on the gate structure to provide stress along the direction parallel to the channel length of the gate structure. The stress helps promote the mobility of the charges in the channel region under the gate structure and improve the electrical performance such as drive current and DIBL of the three-dimensional multi-gate device.
摘要翻译：三维多栅极器件具有硅鳍，栅极结构和应力调节层。栅极结构与硅片的三个表面接触以形成三维栅极结构。应力调整层设置在栅极结构上，以沿与栅极结构的沟道长度平行的方向提供应力。应力有助于提高栅极结构下沟道区域电荷的迁移率，提高三维多栅极器件的驱动电流和DIBL等电气性能。

10. 发明申请

US20070122924A1 METHOD OF FABRICATING METAL OXIDE SEMICONDUCTOR TRANSISTOR 审中-公开
标题翻译：制备金属氧化物半导体晶体管的方法
公开(公告)号：US20070122924A1
公开(公告)日：2007-05-31
申请号：US11669952
申请日：2007-02-01
申请人： Wen-Shiang Liao , Wei-Tsun Shiau
发明人： Wen-Shiang Liao , Wei-Tsun Shiau
IPC分类号： H01L21/00
CPC分类号： H01L21/823418 , H01L21/823814 , H01L29/66636 , H01L29/7834
摘要： A masking layer is formed over a substrate. The substrate and the masking layer are patterned to form trenches that partitions the substrate into first doping type semiconductor strips. An isolation layer is formed inside the trenches such that the surface of the isolation layer is below the upper surface of the first doping type semiconductor strips. A gate oxide layer is formed on the sidewalls of the first doping type semiconductor strips. Gates are formed over the substrate. The gates cover the masking layer above the first doping type semiconductor strips and the isolation layer inside the trenches. The gates are set in a direction perpendicular to the first doping type semiconductor strips. Spacers are formed on the sidewalls of the gates and the first doping type semiconductor strips. Second doping type source/drain regions are formed in the first doping type semiconductor strips on each side of the gates.
摘要翻译：在衬底上形成掩模层。将衬底和掩模层图案化以形成将衬底分隔成第一掺杂型半导体条的沟槽。隔离层形成在沟槽内，使得隔离层的表面在第一掺杂型半导体条的上表面之下。栅极氧化物层形成在第一掺杂型半导体条的侧壁上。盖板形成在基板上。栅极覆盖第一掺杂型半导体条上方的掩模层和沟槽内的隔离层。栅极设置在垂直于第一掺杂型半导体条的方向上。隔板形成在栅极的侧壁和第一掺杂型半导体条上。在栅极的每一侧的第一掺杂型半导体条中形成第二掺杂型源极/漏极区。

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