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1. 发明授权

US07986696B1 Method and apparatus for longest prefix matching 有权
标题翻译：最长前缀匹配的方法和装置
公开(公告)号：US07986696B1
公开(公告)日：2011-07-26
申请号：US12369792
申请日：2009-02-12
申请人： Vladimir Miliavisky , Eyal Oren , Vladimir Kolmanovitch , Alexander Zeltser , Michael Mesh
发明人： Vladimir Miliavisky , Eyal Oren , Vladimir Kolmanovitch , Alexander Zeltser , Michael Mesh
IPC分类号： H04L12/56 , G06F13/00
CPC分类号： H04L45/7457 , H04L45/54 , H04L45/7453
摘要： A lookup table including stored data, the lookup table including a Random Access Memory (RAM) for storing the data, wherein the RAM includes a plurality of windows; and a Ternary Content Addressable Memory (TCAM) for storing indices, each index pointing to the windows, and a method for performing a Longest Prefix Match (LPM) including organizing data in such a lookup table, searching according to a lookup key in the TCAM, receiving a match signal from the TCAM including an index pointing to one of the windows, and searching according to the lookup key in the pointed to window.
摘要翻译：包括存储数据的查找表，查找表包括用于存储数据的随机存取存储器（RAM），其中RAM包括多个窗口; 以及用于存储索引的三进制内容可寻址存储器（TCAM），每个索引指向窗口，以及用于执行包括在这样的查找表中组织数据的最长前缀匹配（LPM）的方法，根据TCAM中的查找键进行搜索从TCAM接收包括指向其中一个窗口的索引的匹配信号，并根据指向窗口中的查找键进行搜索。

2. 发明授权

US08972828B1 High speed interconnect protocol and method 有权
标题翻译：高速互联协议和方法
公开(公告)号：US08972828B1
公开(公告)日：2015-03-03
申请号：US13534835
申请日：2012-06-27
申请人： Niv Margalit , Eyal Oren , Rami Zemach , Dan Zislis
发明人： Niv Margalit , Eyal Oren , Rami Zemach , Dan Zislis
IPC分类号： H03M13/00
CPC分类号： H03M13/333 , H03M13/09 , H03M13/19
摘要： A method of error mitigation for transferring packets over a chip-to-chip data interconnect using a high speed interconnect protocol, the method including grouping a pre-selected number of high speed interconnect protocol words to form a protection frame, adding at least one additional error protection bit to each word in the group, adding a synchronization bit to each word, using the synchronization bit in a first word in each frame for synchronization of the protection frame and detecting and correcting a single bit error in the protection frame using the additional error protection bits, thereby reducing packet drop when the frames are transferred over the high speed data interconnect.
摘要翻译：一种用于使用高速互连协议通过芯片到芯片数据互连传输分组的错误减轻的方法，所述方法包括将预选数量的高速互连协议字分组以形成保护帧，添加至少一个附加错误保护位到组中的每个字，使用每个帧中的第一个字中的同步位来对每个字添加一个同步位，用于保护帧的同步，并使用附加的检测和校正保护帧中的单个位错误错误保护位，从而在通过高速数据互连传输帧时减少数据包丢弃。

3. 发明授权

US07729351B2 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US07729351B2
公开(公告)日：2010-06-01
申请号：US11365017
申请日：2006-03-01
申请人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
发明人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
IPC分类号： H04L12/56 , H04J1/16
CPC分类号： H04L49/1546 , H04L49/201 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/503 , H04L49/506
摘要： An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets. These features can include a recycle path coupling a gather stage circuit and a fetch stage circuit and can include sequence number logic configured to associate sequence numbers with multicast packet headers.
摘要翻译：提供了一种网络路由设备中线路卡的架构。线路卡架构在路由设备和网络之间提供双向接口，两者都接收来自网络的分组，并通过一个或多个连接端口将分组发送到网络。在接收和发送路径中，提供了可以同时在多个分组上操作以确定每个分组的路由目的地的多级并行流水线中的分组处理和路由。线路卡架构的传输路径进一步包含用于组播数据包的处理和复制的附加功能。这些特征可以包括耦合收集阶段电路和获取级电路的再循环路径，并且可以包括被配置为将序列号与多播分组报头相关联的序列号逻辑。

4. 发明授权

US07643486B2 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US07643486B2
公开(公告)日：2010-01-05
申请号：US11242453
申请日：2005-10-03
申请人： David Belz , Garry P. Epps , Michael Laor , Eyal Oren
发明人： David Belz , Garry P. Epps , Michael Laor , Eyal Oren
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/527 , H04L47/10 , H04L47/21 , H04L47/326 , H04L47/50 , H04L47/6215 , H04L49/1546 , H04L49/205 , H04L49/3009 , H04L49/3018 , H04L49/3063 , H04L49/50 , H04L49/552 , H04L49/602 , H04L49/90 , H04L49/9078
摘要： A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in a multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Using bandwidth management techniques, each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port. The destination linecard may be the same physical linecard as that receiving the inbound packet or a different physical linecard. The transmit path includes a buffer/queuing circuit similar to that used in the receive path and can include another pipelined switch. Both enqueuing and dequeuing of packets is accomplished using CoS-based decision making apparatus, congestion avoidance, and bandwidth management hardware.
摘要翻译：用于接收，修改，切换，缓冲，排队和排队数据包以在通信网络中传输的流水线线卡架构。线路卡具有两条路径：从网络将数据包传送到交换机设备的接收路径，以及将交换机传送到网络的数据包的发送路径。在接收路径中，使用可编程数据结构在多级流水线中对接收到的数据包进行处理和切换，以便进行快速表查找和链表遍历。流水线交换机在确定每个数据包的路由目的地时并行操作多个数据包。一旦进行了确定，每个数据包被修改为包含新的路由信息以及额外的标题数据，以帮助通过交换机加速速度。使用带宽管理技术，每个数据包然后被缓冲并排入队列，以便通过交换结构传输到连接到适当目标端口的线卡。目的线路卡可能与接收入站分组或不同物理线卡一样的物理线卡。发送路径包括类似于在接收路径中使用的缓冲器/排队电路，并且可以包括另一流水线开关。使用基于CoS的决策设备，拥塞避免和带宽管理硬件来实现分组的入队和出队。

5. 发明申请

US20070195773A1 Pipelined packet switching and queuing architecture 有权
公开(公告)号：US20070195773A1
公开(公告)日：2007-08-23
申请号：US11358860
申请日：2006-02-21
申请人： Mohammed Tatar , Garry Epps , Oded Trainin , Eyal Oren , Cedrik Begin
发明人： Mohammed Tatar , Garry Epps , Oded Trainin , Eyal Oren , Cedrik Begin
IPC分类号： H04L12/56
CPC分类号： H04L49/1546 , H04L49/201 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/503 , H04L49/506
摘要： An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets.

6. 发明授权

US06961808B1 Method and apparatus for implementing and using multiple virtual portions of physical associative memories 有权
标题翻译：用于实现和使用物理关联存储器的多个虚拟部分的方法和装置
公开(公告)号：US06961808B1
公开(公告)日：2005-11-01
申请号：US10042836
申请日：2002-01-08
申请人： Eyal Oren , David E. Belz
发明人： Eyal Oren , David E. Belz
IPC分类号： G06F12/00 , G06F17/30
CPC分类号： G06F17/30985
摘要： Methods and apparatus are disclosed for implementing and using multiple virtual portions of an associative memory. An associative memory is programmed with multiple sets of entries, each of the multiple sets of entries including a different unique decoder field. A piece of information is received including a data item. A decoder field is identified. The decoder field and the data item are typically included in a lookup word used in a lookup operation in the associated memory, with the decoder field identifying which of the multiple sets of entries to search based on the data item. In one implementation, a nested condition associated with the data item is identified, and in response, multiple lookup words are generated with a predefined set of decoder fields for the data item. Multiple levels of decoder fields may be used to identify multiple subsets of entries within one of the multiple sets of entries.
摘要翻译：公开了用于实现和使用关联存储器的多个虚拟部分的方法和装置。关联存储器被编程有多组条目，多组条目中的每一个包括不同的唯一解码器字段。接收包括数据项的信息。识别解码器字段。解码器字段和数据项通常包括在相关存储器中的查找操作中使用的查找字中，解码器字段根据该数据项标识要搜索的多组条目中的哪一个。在一个实现中，识别与数据项相关联的嵌套条件，并且作为响应，用数据项的预定义的解码器字段组生成多个查找字。可以使用多级解码器字段来标识多组条目之一内的条目的多个子集。

7. 发明授权

US08571024B2 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US08571024B2
公开(公告)日：2013-10-29
申请号：US12952601
申请日：2010-11-23
申请人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
发明人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
IPC分类号： H04L12/28 , H04J1/16
CPC分类号： H04L49/1546 , H04L49/201 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/503 , H04L49/506
摘要： An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets.
摘要翻译：提供了一种网络路由设备中线路卡的架构。线路卡架构在路由设备和网络之间提供双向接口，两者都接收来自网络的分组，并通过一个或多个连接端口将分组发送到网络。在接收和发送路径中，提供了可以同时在多个分组上操作以确定每个分组的路由目的地的多级并行流水线中的分组处理和路由。一旦进行了路由目的地确定，线路卡架构将为要修改的每个接收的分组提供包含新的路由信息和附加的头部数据，以便于通过交换结构的分组传输。线路卡架构进一步提供使用带宽管理技术，以便缓冲和排队每个分组以便通过交换结构传输到相应的目的地端口。线路卡架构的传输路径进一步包含用于组播数据包的处理和复制的附加功能。

8. 发明申请

US20120106562A1 ROUTER AND SWITCH ARCHITECTURE 有权
标题翻译：路由器和交换机架构
公开(公告)号：US20120106562A1
公开(公告)日：2012-05-03
申请号：US13281940
申请日：2011-10-26
申请人： Michael Laor , Eyal Oren , Vladimir Miliavsky
发明人： Michael Laor , Eyal Oren , Vladimir Miliavsky
IPC分类号： H04L12/56
CPC分类号： H04L45/60 , H04L49/10 , H04L49/3009
摘要： A packet switching system for a packet transfer network, the system having an architecture including a plurality of line cards, each including an ingress path pipeline, with processing elements, and an egress buffer, and an electro-optical In/Out (IO) interconnect coupling the line cards to one another in a full mesh connectivity, in the absence of a switch fabric, wherein the ingress path pipeline of each line card is coupled by means of the electro-optical IO interconnect to the egress buffer of each of the plurality of line cards.
摘要翻译：一种用于分组传送网络的分组交换系统，该系统具有包括多个线路卡的架构，每个线路卡包括具有处理单元的入口路径管道和出口缓冲器以及电光输入/输出（IO）互连在不存在交换结构的情况下，以完全网状连接方式将线路卡彼此耦合，其中每个线路卡的入口路径管线通过电光IO互连耦合到多个的每个的出口缓冲器的线卡。

9. 发明授权

US07864791B2 Pipelined packet switching and queuing architecture 有权
标题翻译：流水线分组交换和排队架构
公开(公告)号：US07864791B2
公开(公告)日：2011-01-04
申请号：US11931527
申请日：2007-10-31
申请人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
发明人： Mohammed I. Tatar , Garry P. Epps , Oded Trainin , Eyal Oren , Cedrik Begin
IPC分类号： H04L12/56 , H04J1/16
CPC分类号： H04L49/1546 , H04L49/201 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/503 , H04L49/506
摘要： An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets.
摘要翻译：提供了一种网络路由设备中线路卡的架构。线路卡架构在路由设备和网络之间提供双向接口，两者都接收来自网络的分组，并通过一个或多个连接端口将分组发送到网络。在接收和发送路径中，提供了可以同时在多个分组上操作以确定每个分组的路由目的地的多级并行流水线中的分组处理和路由。一旦进行了路由目的地确定，线路卡架构将为要修改的每个接收的分组提供包含新的路由信息和附加的头部数据，以便于通过交换结构的分组传输。线路卡架构进一步提供使用带宽管理技术，以便缓冲和排队每个分组以便通过交换结构传输到相应的目的地端口。线路卡架构的传输路径进一步包含用于组播数据包的处理和复制的附加功能。

10. 发明授权

US07599287B2 Tokens in token buckets maintained among primary and secondary storages 有权
标题翻译：令牌桶中的令牌在主存储和辅助存储之间保持
公开(公告)号：US07599287B2
公开(公告)日：2009-10-06
申请号：US11271247
申请日：2005-11-11
申请人： James Fraser Testa , Eyal Oren , Earl T. Cohen
发明人： James Fraser Testa , Eyal Oren , Earl T. Cohen
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/215
摘要： Token buckets are used in a computer or communications system for controlling rates at which corresponding items are processed. The number of tokens in a token bucket identifies the amount of processing that is available for the corresponding item. Instead of storing the value of a token bucket as a single value in a single memory location as traditionally done, the value of a token bucket is stored across multiple storage locations, such as in on-chip storage and in off-chip storage (e.g., in a memory device). An indication (e.g., one or more bits) can also be stored on chip to identify whether or not the off-chip stored value is zero and/or of at least of a certain magnitude such that it may be readily determined whether there are sufficient tokens to process an item without accessing the off-chip storage.
摘要翻译：在计算机或通信系统中使用令牌桶来控制处理相应项目的速率。令牌桶中的令牌数量标识可用于相应项目的处理量。令牌桶的值不像传统上将单个值存储在单个存储单元中而不是将令牌桶的值存储在多个存储位置之间，例如片上存储和片外存储（例如，，在存储设备中）。指示（例如，一个或多个比特）也可以存储在芯片上以识别片外存储的值是否为零和/或至少具有一定幅度，使得可以容易地确定是否有足够的令牌处理项目而不访问片外存储。

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