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1. 发明申请

US20100290528A1 REAL-TIME VIDEO IMAGE PROCESSING 有权
标题翻译：实时视频图像处理
公开(公告)号：US20100290528A1
公开(公告)日：2010-11-18
申请号：US12729499
申请日：2010-03-23
申请人： Vivekanand CHENGALVALA , Ran Katzur , Djordje Senicic
发明人： Vivekanand CHENGALVALA , Ran Katzur , Djordje Senicic
IPC分类号： H04N7/26
CPC分类号： H04N19/00127 , H04N19/132 , H04N19/156 , H04N19/159 , H04N19/176 , H04N19/85
摘要： A video processing device includes a video preprocessor and a video processor. The video processor is configured to facilitate inputting preprocessed digital video data ready for further processing by an encoder or a transcoder, compressing the preprocessed digital video data to form compressed digital video data, and outputting the compressed digital video data. The video preprocessor operable to receive digital video raw data, configured to facilitate preprocessing a macroblock of the digital video raw data so as to output the preprocessed digital video data ready for an encoder or transcoder of the video processor when the macroblock does not indicate SKIP, and not preprocessing the macroblock of the digital video raw data when the macroblock is a SKIP macroblock indicating SKIP, but jumping to process the SKIP macroblock by an entropy encoder of the video processor instead.
摘要翻译：视频处理设备包括视频预处理器和视频处理器。视频处理器被配置为便于输入预处理的数字视频数据，准备好由编码器或代码转换器进一步处理，压缩预处理的数字视频数据以形成压缩的数字视频数据，并输出压缩的数字视频数据。所述视频预处理器可操作以接收数字视频原始数据，其被配置为便于对所述数字视频原始数据的宏块进行预处理，以便当所述宏块不指示SKIP时，输出预处理的数字视频数据，供所述视频处理器的编码器或代码转换器准备，并且当宏块是指示SKIP的SKIP宏块时，不是预处理数字视频原始数据的宏块，而是由视频处理器的熵编码器跳转到处理SKIP宏块。

2. 发明授权

US08644389B2 Real-time video image processing 有权
标题翻译：实时视频图像处理
公开(公告)号：US08644389B2
公开(公告)日：2014-02-04
申请号：US12729499
申请日：2010-03-23
申请人： Vivekanand Chengalvala , Ran Katzur , Djordje Senicic
发明人： Vivekanand Chengalvala , Ran Katzur , Djordje Senicic
IPC分类号： H04B1/66 , H04N7/12 , H04N11/02 , H04N11/04 , H04N7/26
CPC分类号： H04N19/00127 , H04N19/132 , H04N19/156 , H04N19/159 , H04N19/176 , H04N19/85
摘要： A video processing device includes a video preprocessor and a video processor. The video processor is configured to facilitate inputting preprocessed digital video data ready for further processing by an encoder or a transcoder, compressing the preprocessed digital video data to form compressed digital video data, and outputting the compressed digital video data. The video preprocessor operable to receive digital video raw data, configured to facilitate preprocessing a macroblock of the digital video raw data so as to output the preprocessed digital video data ready for an encoder or transcoder of the video processor when the macroblock does not indicate SKIP, and not preprocessing the macroblock of the digital video raw data when the macroblock is a SKIP macroblock indicating SKIP, but jumping to process the SKIP macroblock by an entropy encoder of the video processor instead.
摘要翻译：视频处理设备包括视频预处理器和视频处理器。视频处理器被配置为便于输入预处理的数字视频数据，准备好由编码器或代码转换器进一步处理，压缩预处理的数字视频数据以形成压缩的数字视频数据，并输出压缩的数字视频数据。所述视频预处理器可操作以接收数字视频原始数据，其被配置为便于对所述数字视频原始数据的宏块进行预处理，以便当所述宏块不指示SKIP时，输出预处理的数字视频数据，供所述视频处理器的编码器或代码转换器准备，并且当宏块是指示SKIP的SKIP宏块时，不是预处理数字视频原始数据的宏块，而是由视频处理器的熵编码器跳转到处理SKIP宏块。

3. 发明申请

US20120243616A1 System and Method for Adaptively Allocating Resources in a Transcoder 审中-公开
标题翻译：在转码器中自适应分配资源的系统和方法
公开(公告)号：US20120243616A1
公开(公告)日：2012-09-27
申请号：US13486480
申请日：2012-06-01
申请人： Vivekanand Chengalvala , Djordje Senicic
发明人： Vivekanand Chengalvala , Djordje Senicic
IPC分类号： H04N7/12
CPC分类号： H04N19/423 , H04N19/40 , H04N19/42 , H04N19/44 , H04N19/70
摘要： An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.
摘要翻译：提供了一种自适应代码转换器，其包括：包含多个解码器缓冲器以存储输入数据分组的共享存储器;多个解码器实例，用于控制解码过程以基于输入数据分组生成图像原始数据;以及多个编码器实例被配置为基于所述图像原始数据来控制编码处理以生成输出分组; 以及包含多个处理核心的数据处理元件和核心控制器。每个解码器实例与编码器实例配对; 并且每个解码器缓冲器与解码器实例相关联。每个解码器缓冲器包括监视元件以监视相应的解码器缓冲器，并提供对应于解码器缓冲器的状态的缓冲器数据。每个编码器实例与处理核心相关联; 并且核心控制器使用缓冲器数据将每个解码器实例与处理核心相关联。

4. 发明授权

US08228980B2 Media gateway with overlay channels 有权
标题翻译：带重叠频道的媒体网关
公开(公告)号：US08228980B2
公开(公告)日：2012-07-24
申请号：US12474807
申请日：2009-05-29
申请人： Raghu Nambiath , Vivekanand Chengalvala , Djordje Senicic , Nagashankar Chandrashekar
发明人： Raghu Nambiath , Vivekanand Chengalvala , Djordje Senicic , Nagashankar Chandrashekar
IPC分类号： H04N7/12
CPC分类号： H04N21/42653 , H04N21/4316 , H04N21/4788 , H04N21/4882
摘要： A network media gateway is disclosed with a processor configured to include a plurality of decoder channels, a plurality of overlay channels, an overlay renderer, a video mixer, and an encoder channel. A digital signal processor embedded in a network media gateway is also disclosed, and a mixing method implemented on a digital signal processor is also disclosed.
摘要翻译：公开了一种网络媒体网关，处理器被配置为包括多个解码器信道，多个覆盖信道，覆盖渲染器，视频混合器和编码器信道。还公开了嵌入在网络媒体网关中的数字信号处理器，并且还公开了在数字信号处理器上实现的混合方法。

5. 发明授权

US09271007B2 System and method for adaptively allocating resources in a transcoder 有权
标题翻译：用于在代码转换器中自适应地分配资源的系统和方法
公开(公告)号：US09271007B2
公开(公告)日：2016-02-23
申请号：US13486480
申请日：2012-06-01
申请人： Vivekanand Chengalvala , Djordje Senicic
发明人： Vivekanand Chengalvala , Djordje Senicic
IPC分类号： H04N11/02 , H04N19/40 , H04N19/42
CPC分类号： H04N19/423 , H04N19/40 , H04N19/42 , H04N19/44 , H04N19/70
摘要： An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.
摘要翻译：提供了一种自适应代码转换器，其包括：包含多个解码器缓冲器以存储输入数据分组的共享存储器;多个解码器实例，用于控制解码过程以基于输入数据分组生成图像原始数据;以及多个编码器实例被配置为基于所述图像原始数据来控制编码处理以生成输出分组; 以及包含多个处理核心的数据处理元件和核心控制器。每个解码器实例与编码器实例配对; 并且每个解码器缓冲器与解码器实例相关联。每个解码器缓冲器包括监视元件以监视相应的解码器缓冲器，并提供对应于解码器缓冲器的状态的缓冲器数据。每个编码器实例与处理核心相关联; 并且核心控制器使用缓冲器数据将每个解码器实例与处理核心相关联。

6. 发明授权

US08300703B2 System and method for adaptively allocating resources in a transcoder 有权
标题翻译：用于在代码转换器中自适应地分配资源的系统和方法
公开(公告)号：US08300703B2
公开(公告)日：2012-10-30
申请号：US12564532
申请日：2009-09-22
申请人： Vivekanand Chengalvala , Djordje Senicic
发明人： Vivekanand Chengalvala , Djordje Senicic
IPC分类号： H04N7/12
CPC分类号： H04N19/423 , H04N19/40 , H04N19/42 , H04N19/44 , H04N19/70
摘要： An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.
摘要翻译：提供了一种自适应代码转换器，其包括：包含多个解码器缓冲器以存储输入数据分组的共享存储器;多个解码器实例，用于控制解码过程以基于输入数据分组生成图像原始数据;以及多个编码器实例被配置为基于所述图像原始数据来控制编码处理以生成输出分组; 以及包含多个处理核心的数据处理元件和核心控制器。每个解码器实例与编码器实例配对; 并且每个解码器缓冲器与解码器实例相关联。每个解码器缓冲器包括监视元件以监视相应的解码器缓冲器，并提供对应于解码器缓冲器的状态的缓冲器数据。每个编码器实例与处理核心相关联; 并且核心控制器使用缓冲器数据将每个解码器实例与处理核心相关联。

7. 发明申请

US20110069750A1 SYSTEM AND METHOD FOR ADAPTIVELY ALLOCATING RESOURCES IN A TRANSCODER 有权
标题翻译：用于在移动平台中自适应分配资源的系统和方法
公开(公告)号：US20110069750A1
公开(公告)日：2011-03-24
申请号：US12564532
申请日：2009-09-22
申请人： Vivekanand CHENGALVALA , Djordje Senicic
发明人： Vivekanand CHENGALVALA , Djordje Senicic
IPC分类号： H04N7/12 , H04N17/00 , G06F9/46
CPC分类号： H04N19/423 , H04N19/40 , H04N19/42 , H04N19/44 , H04N19/70
摘要： An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.
摘要翻译：提供了一种自适应代码转换器，其包括：包含多个解码器缓冲器以存储输入数据分组的共享存储器;多个解码器实例，用于控制解码过程以基于输入数据分组生成图像原始数据;以及多个编码器实例被配置为基于所述图像原始数据来控制编码处理以生成输出分组; 以及包含多个处理核心的数据处理元件和核心控制器。每个解码器实例与编码器实例配对; 并且每个解码器缓冲器与解码器实例相关联。每个解码器缓冲器包括监视元件以监视相应的解码器缓冲器，并提供对应于解码器缓冲器的状态的缓冲器数据。每个编码器实例与处理核心相关联; 并且核心控制器使用缓冲器数据将每个解码器实例与处理核心相关联。

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