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1. 发明授权

US09990201B2 Multiplication instruction for which execution completes without writing a carry flag 有权
公开(公告)号：US09990201B2
公开(公告)日：2018-06-05
申请号：US12645383
申请日：2009-12-22
申请人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdine Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
发明人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdine Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30094 , G06F9/30014
摘要： A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

2. 发明申请

US20110153994A1 Multiplication Instruction for Which Execution Completes Without Writing a Carry Flag 有权
标题翻译：执行完成的乘法指令不写入进位标志
公开(公告)号：US20110153994A1
公开(公告)日：2011-06-23
申请号：US12645383
申请日：2009-12-22
申请人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdinc Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
发明人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdinc Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
IPC分类号： G06F9/302
CPC分类号： G06F9/30094 , G06F9/30014
摘要： A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.
摘要翻译：一方面的方法可以包括接收乘法指令。乘法指令可以指示第一源操作数和第二源操作数。第一和第二源操作数的乘积可以存储在由乘法指令指示的一个或多个目的地操作数中。乘法指令的执行可以在不写进位标志的情况下完成。还公开了其它方法，以及机器可读介质上的装置，系统和指令。

3. 发明授权

US08504804B2 Managing multiple threads in a single pipeline 有权
标题翻译：在单个管道中管理多个线程
公开(公告)号：US08504804B2
公开(公告)日：2013-08-06
申请号：US13613820
申请日：2012-09-13
申请人： Matthew Merten , Avinash Sodani , James Hadley , Alexandre Farcy , Iredamola Olopade
发明人： Matthew Merten , Avinash Sodani , James Hadley , Alexandre Farcy , Iredamola Olopade
IPC分类号： G06F15/00 , G06F9/40 , G06F9/30
CPC分类号： G06F9/3851
摘要： In one embodiment, the present invention includes a method for determining if an instruction of a first thread dispatched from a first queue associated with the first thread is stalled in a pipestage of a pipeline, and if so, dispatching an instruction of a second thread from a second queue associated with the second thread to the pipeline if the second thread is not stalled. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定从与第一线程相关联的第一队列调度的第一线程的指令是否在流水线的分支中被停止的方法，如果是，则将第二线程的指令从如果第二线程没有停止，则与第二线程相关联的第二队列到管道。描述和要求保护其他实施例。

4. 发明申请

US20070300049A1 Technique to perform three-source operations 有权
标题翻译：执行三源操作的技术
公开(公告)号：US20070300049A1
公开(公告)日：2007-12-27
申请号：US11477074
申请日：2006-06-27
申请人： Avinash Sodani , Stephan Jourdan , Alexandre Farcy , Per Hammarlund
发明人： Avinash Sodani , Stephan Jourdan , Alexandre Farcy , Per Hammarlund
IPC分类号： G06F9/44
CPC分类号： G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3017 , G06F9/45504
摘要： A technique to perform three-source instructions. At least one embodiment of the invention relates to converting a three-source instruction into at least two instructions identifying no more than two source values.
摘要翻译：一种执行三源指令的技术。本发明的至少一个实施例涉及将三源指令转换成标识不超过两个源值的至少两个指令。

5. 发明申请

US20070157006A1 Method and apparatus for microarchitecture partitioning of execution clusters 有权
标题翻译：执行集群的微架构划分方法和装置
公开(公告)号：US20070157006A1
公开(公告)日：2007-07-05
申请号：US11322768
申请日：2005-12-30
申请人： Stephan Jourdan , Avinash Sodani , Alexandre Farcy , Per Hammarlund , Sebastien Hily , Mark Davis
发明人： Stephan Jourdan , Avinash Sodani , Alexandre Farcy , Per Hammarlund , Sebastien Hily , Mark Davis
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30101 , G06F9/3012 , G06F9/3828 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3885 , G06F9/3891
摘要： Microarchitecture policies and structures partition execution resource clusters. In disclosed microarchitecture embodiments, micro-operations representing a sequential instruction ordering are partitioned into a two sets. To one set of micro-operations execution resources are allocated from a cluster of execution resources that can perform memory access operations but not branching operations. To the other set of micro-operations execution resources are allocated from a cluster of execution resources that can perform branching operations but not memory access operations. The first and second sets of micro-operations may be executed out of sequential order but are retired to represent their sequential instruction ordering.
摘要翻译：微架构策略和结构分区执行资源集群。在公开的微架构实施例中，表示顺序指令排序的微操作被划分成两组。对于一组微操作执行资源从可执行存储器访问操作而不是分支操作的执行资源集群分配。对另一组微操作执行资源从可执行分支操作而不是存储器访问操作的执行资源集群分配。第一组和第二组微操作可以按顺序执行，但是退休以表示其顺序指令排序。

6. 发明申请

US20050149912A1 Dynamic online optimizer 审中-公开
标题翻译：动态在线优化器
公开(公告)号：US20050149912A1
公开(公告)日：2005-07-07
申请号：US10748284
申请日：2003-12-29
申请人： Alexandre Farcy , Stephan Jourdan , Avinash Sodani , Per Hammarlund
发明人： Alexandre Farcy , Stephan Jourdan , Avinash Sodani , Per Hammarlund
IPC分类号： G06F9/38 , G06F9/44
CPC分类号： G06F9/3808 , G06F8/443
摘要： A system and method for optimizing a series of traces to be executed by a processing core is disclosed. The lines of a trace are sent to an optimizer each time they are sent to a processing core to be executed. Runtime information may be collected on a line of a trace each time that trace is executed by a processing core. The runtime information may be used by the optimizer to better optimize the micro-operations of the lines of the trace. The optimizer optimizes a trace each time the trace is executed to improve the efficiency of future iterations of the trace. Most of the optimizations result in a reduction of the number of μops within the trace. The optimizer may optimize two or more lines at a time in order to find more opportunities to remove μops and shorten the trace. The two lines may be alternately offset so that each line has the maximum allowed number of micro-operations.
摘要翻译：公开了一种用于优化要由处理核执行的一系列迹线的系统和方法。每次将跟踪的行发送到执行处理核心时，都将其发送到优化器。每次由处理核心执行跟踪时，运行时信息可以在跟踪线上收集。优化器可以使用运行时信息来更好地优化跟踪线的微操作。优化器每次执行跟踪时优化跟踪，以提高跟踪的未来迭代的效率。大多数优化导致跟踪中的muops数量减少。优化器可以一次优化两行或更多行，以便找到更多机会删除muops并缩短跟踪。两条线可以交替地偏移，使得每条线具有允许的最大微操作数。

7. 发明授权

US08521993B2 Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor 有权
标题翻译：在处理器流水线中提供线程公平性，以响应于处理器流水线中的停顿而使用失速循环计数器
公开(公告)号：US08521993B2
公开(公告)日：2013-08-27
申请号：US11784864
申请日：2007-04-09
申请人： Morris Marden , Matthew Merten , Alexandre Farcy , Avinash Sodani , James Hadley , Ilhyun Kim
发明人： Morris Marden , Matthew Merten , Alexandre Farcy , Avinash Sodani , James Hadley , Ilhyun Kim
IPC分类号： G06F9/40
CPC分类号： G06F9/50 , G06F9/30101 , G06F9/3851 , G06F2209/5014
摘要： A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.
摘要翻译：这里描述用于在多处理元件环境中提供公平性的方法和装置。掩模元件被用于具有每个处理元件的保留站的相关部分，同时仍然允许对保留站条目的另一部分的公共访问。此外，偏置逻辑偏离了管线中的处理元件的选择，远离与阻塞档位相关联的处理元件，以提供管道的公平利用。

8. 发明申请

US20110055524A1 PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR 审中-公开
公开(公告)号：US20110055524A1
公开(公告)日：2011-03-03
申请号：US12941637
申请日：2010-11-08
申请人： Morris Marden , Matthew Merten , Alexandre Farcy , Avinash Sodani , James Hadley , Ilhyun Kim
发明人： Morris Marden , Matthew Merten , Alexandre Farcy , Avinash Sodani , James Hadley , Ilhyun Kim
IPC分类号： G06F9/30
CPC分类号： G06F9/50 , G06F9/30101 , G06F9/3851 , G06F2209/5014
摘要： A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.

9. 发明申请

US20080065865A1 In-use bits for efficient instruction fetch operations 审中-公开
标题翻译：用于有效指令提取操作的使用位
公开(公告)号：US20080065865A1
公开(公告)日：2008-03-13
申请号：US11518103
申请日：2006-09-08
申请人： Ilhyun Kim , Stephan Jourdan , Alexandre Farcy , Bret Toll
发明人： Ilhyun Kim , Stephan Jourdan , Alexandre Farcy , Bret Toll
IPC分类号： G06F9/44
CPC分类号： G06F12/1027 , G06F9/3814
摘要： Methods and apparatus to perform efficient instruction fetch operations are described. In an embodiment, one or more bits are utilized to determine when to modify an entry in a storage unit of a processor. Other embodiments are also described.
摘要翻译：描述执行有效的指令获取操作的方法和装置。在一个实施例中，利用一个或多个比特来确定何时修改处理器的存储单元中的条目。还描述了其它实施例。

10. 发明授权

US08438369B2 Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor 有权
标题翻译：通过在超线程微处理器中使用失速循环计数器，将选择偏离延迟线程来提供线程公平性
公开(公告)号：US08438369B2
公开(公告)日：2013-05-07
申请号：US12941615
申请日：2010-11-08
申请人： Morris Marden , Matthew Merten , Alexandre Farcy , Avinash Sodani , James Hadley , Ilhyun Kim
发明人： Morris Marden , Matthew Merten , Alexandre Farcy , Avinash Sodani , James Hadley , Ilhyun Kim
IPC分类号： G06F9/40
CPC分类号： G06F9/50 , G06F9/30101 , G06F9/3851 , G06F2209/5014
摘要： A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.
摘要翻译：这里描述用于在多处理元件环境中提供公平性的方法和装置。掩模元件被用于具有每个处理元件的保留站的相关部分，同时仍然允许对保留站条目的另一部分的公共访问。此外，偏置逻辑偏离了管线中的处理元件的选择，远离与阻塞档位相关联的处理元件，以提供管道的公平利用。

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