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1. 发明申请

US20070006192A1 Intermediate representation for multiple exception handling models 有权
标题翻译：多个异常处理模型的中间表示
公开(公告)号：US20070006192A1
公开(公告)日：2007-01-04
申请号：US11505090
申请日：2006-08-15
申请人： Vinod Grover , Akella Sastry
发明人： Vinod Grover , Akella Sastry
IPC分类号： G06F9/45
CPC分类号： G06F8/20 , G06F8/423
摘要： As described herein, an intermediate representation of a source code file may be used to explicitly express exception handling control flow prior to generating object code for the source code. As further described herein, a single uniform set of instructions of the intermediate representation may be used for expressing multiple different exception handling mechanisms related to multiple different programming languages. The intermediate form of the exception handling instructions may be generated by translating an intermediate language representation of the source code file. Representations of the source code in multiple different intermediate languages may be translated to a single uniform set of instructions of the intermediate representation. The intermediate form of the exception handling instructions may then be used by software development tools for such tasks as code generation, code optimization, code analysis etc. Thus, the same methods for code optimizations, analysis and generation may be used for intermediate representations of multiple different languages.
摘要翻译：如本文所述，源代码文件的中间表示可以用于在为源代码生成目标代码之前显式表达异常处理控制流程。如本文进一步描述的，中间表示的单个均匀的指令集可以用于表示与多个不同的编程语言相关的多个不同的异常处理机制。可以通过翻译源代码文件的中间语言表示来生成异常处理指令的中间形式。可以将多个不同中间语言的源代码的表示形式转换为中间表示的单个均匀指令集。异常处理指令的中间形式然后可以由软件开发工具用于诸如代码生成，代码优化，代码分析等任务。因此，用于代码优化，分析和生成的相同方法可以用于多个的中间表示不同的语言。

2. 发明授权

US08984498B2 Variance analysis for translating CUDA code for execution by a general purpose processor 有权
标题翻译：用于翻译CUDA代码以供通用处理器执行的方差分析
公开(公告)号：US08984498B2
公开(公告)日：2015-03-17
申请号：US12415090
申请日：2009-03-31
申请人： Vinod Grover , Bastiaan Joannes Matheus Aarts , Michael Murphy
发明人： Vinod Grover , Bastiaan Joannes Matheus Aarts , Michael Murphy
IPC分类号： G06F9/45
CPC分类号： G06F9/45537 , G06F8/45 , G06F8/456 , G06F9/4843 , G06F11/261 , G06F12/0253
摘要： One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU.
摘要翻译：本发明的一个实施例提出了一种用于翻译使用并行编程模型编写的应用程序的技术，用于在多核图形处理单元（GPU）上执行以由通用中央处理单元（CPU）执行。依赖于多核GPU的特定功能的应用程序的部分由翻译器转换，以供通用CPU执行。应用程序被划分为独立于同步的指令的区域。指令被分类为在区域之间共享的收敛或发散和不同的存储器引用。插入线程循环以确保在通用CPU执行期间在不同线程之间正确共享内存。

3. 发明申请

US20120254875A1 Method for Transforming a Multithreaded Program for General Execution 有权
标题翻译：用于转换多线程程序进行一般执行的方法
公开(公告)号：US20120254875A1
公开(公告)日：2012-10-04
申请号：US13076258
申请日：2011-03-30
申请人： Jaydeep MARATHE , Vinod Grover
发明人： Jaydeep MARATHE , Vinod Grover
IPC分类号： G06F9/46
CPC分类号： G06F8/72 , G06F9/522
摘要： A technique is disclosed for executing a program designed for multi-threaded operation on a general purpose processor. Original source code for the program is transformed from a multi-threaded structure into a computationally equivalent single-threaded structure. A transform operation modifies the original source code to insert code constructs for serial thread execution. The transform operation also replaces synchronization barrier constructs in the original source code with synchronization barrier code that is configured to facilitate serialization. The transformed source code may then be conventionally compiled and advantageously executed on the general purpose processor.
摘要翻译：公开了一种用于在通用处理器上执行针对多线程操作设计的程序的技术。程序的原始源代码从多线程结构转换为计算等效的单线程结构。转换操作修改原始源代码以插入用于串行线程执行的代码结构。变换操作还用原始源代码中的同步屏障代码替代配置为便于序列化的同步屏障代码。然后可以在通用处理器上常规地编译和有利地执行变换的源代码。

4. 发明申请

US20110145637A1 Performing Mode Switching In An Unbounded Transactional Memory (UTM) System 有权
标题翻译：无限制事务内存（UTM）系统中的执行模式切换
公开(公告)号：US20110145637A1
公开(公告)日：2011-06-16
申请号：US12638181
申请日：2009-12-15
申请人： Jan Gray , Martin Taillefer , Yossi Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod Grover , Mike Magruder , Matt Tolton , Bratin Saha , Gad Sheaffer , Vadim Bassin
发明人： Jan Gray , Martin Taillefer , Yossi Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod Grover , Mike Magruder , Matt Tolton , Bratin Saha , Gad Sheaffer , Vadim Bassin
IPC分类号： G06F12/00 , G06F12/08 , G06F11/14
CPC分类号： G06F12/0815 , G06F9/467 , G06F11/141
摘要： In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在具有多个事务执行模式的无界事务存储器（UTM）系统中选择开始第一事务的第一事务执行模式的方法。这些事务执行模式包括在处理器的高速缓冲存储器内执行的硬件模式，使用处理器的事务硬件执行的硬件辅助模式以及软件缓冲器，以及在没有事务性硬件的情况下执行的软件事务存储器（STM）模式。如果在STM模式下没有执行等待事务，则可以将第一事务执行模式选择为硬件模式的最高执行模式，否则可以选择较低的执行模式。描述和要求保护其他实施例。

5. 发明申请

US20050273777A1 Efficient construction of pruned SSA form 有权
标题翻译：修剪SSA形式的有效建设
公开(公告)号：US20050273777A1
公开(公告)日：2005-12-08
申请号：US10863000
申请日：2004-06-07
申请人： Vinod Grover , Weiping Hu
发明人： Vinod Grover , Weiping Hu
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： Intermediate representations of computer code are efficiently generated. More particularly, methods described herein may be used to construct a static single assignment representation of computer code without unnecessary phi-function nodes. Potentially necessary phi-function node assignments may be analyzed to determine whether they directly reach a non-phi use or a necessary phi-use of a corresponding variable. Those that ultimately reach such a use may be determined to be necessary and a pruned static single assignment may be constructed by including those potentially necessary phi-functions determined to be in fact necessary. Also, some phi-function nodes may be determined to be necessary based on their dependency relationship to other phi-functions previously determined to be necessary (e.g., because they directly reach a non-phi use). A phi-function dependency graph may be used to record dependency relationships between phi-function nodes. The analysis can proceed during a forward walk of a control flow representation of the program.
摘要翻译：有效地生成计算机代码的中间表示。更具体地，本文描述的方法可以用于构造计算机代码的静态单分配表示，而不需要不必要的功能节点。可能分析潜在必需的phi函数节点分配，以确定它们是否直接达到非phi使用或相应变量的必要phi使用。最终达到这种用途的那些可以被确定为必要的，并且修剪的静态单个分配可以通过包括被确定为实际需要的那些潜在必要的phi函数来构造。此外，可以基于它们与先前确定为必需的其他phi函数的依赖关系（例如，因为它们直接达到非phi使用）而确定一些phi函数节点是必要的。 phi函数依赖图可用于记录phi函数节点之间的依赖关系。分析可以在程序的控制流表示的向前行进期间进行。

6. 发明授权

US08365016B2 Performing mode switching in an unbounded transactional memory (UTM) system 有权
标题翻译：在无界事务内存（UTM）系统中执行模式切换
公开(公告)号：US08365016B2
公开(公告)日：2013-01-29
申请号：US13307492
申请日：2011-11-30
申请人： Jan Gray , Martin Taillefer , Yossi Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod Grover , Mike Magruder , Matt Tolton , Bratin Saha , Gad Sheaffer , Vadim Bassin
发明人： Jan Gray , Martin Taillefer , Yossi Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod Grover , Mike Magruder , Matt Tolton , Bratin Saha , Gad Sheaffer , Vadim Bassin
IPC分类号： G06F11/00
CPC分类号： G06F12/0815 , G06F9/467 , G06F11/141
摘要： In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在具有多个事务执行模式的无界事务存储器（UTM）系统中选择开始第一事务的第一事务执行模式的方法。这些事务执行模式包括在处理器的高速缓冲存储器内执行的硬件模式，使用处理器的事务硬件执行的硬件辅助模式以及软件缓冲器，以及在没有事务性硬件的情况下执行的软件事务存储器（STM）模式。如果在STM模式下没有执行等待事务，则可以将第一事务执行模式选择为硬件模式的最高执行模式，否则可以选择较低的执行模式。描述和要求保护其他实施例。

7. 发明申请

US20090259828A1 EXECUTION OF RETARGETTED GRAPHICS PROCESSOR ACCELERATED CODE BY A GENERAL PURPOSE PROCESSOR 有权
标题翻译：一般用途处理器执行缩略图处理程序加速代码
公开(公告)号：US20090259828A1
公开(公告)日：2009-10-15
申请号：US12408559
申请日：2009-03-20
申请人： Vinod Grover , Bastiaan Joannes Matheus Aarts , Michael Murphy , Jayant B. Kolhe , John Bryan Pormann , Douglas Saylor
发明人： Vinod Grover , Bastiaan Joannes Matheus Aarts , Michael Murphy , Jayant B. Kolhe , John Bryan Pormann , Douglas Saylor
IPC分类号： G06F9/45 , G06F9/30
CPC分类号： G06F9/45537 , G06F8/45 , G06F8/456 , G06F9/4843 , G06F11/261 , G06F12/0253
摘要： One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU.
摘要翻译：本发明的一个实施例提出了一种用于翻译使用并行编程模型编写的应用程序的技术，用于在多核图形处理单元（GPU）上执行以由通用中央处理单元（CPU）执行。依赖于多核GPU的特定功能的应用程序的部分由翻译器转换，以供通用CPU执行。应用程序被划分为独立于同步的指令的区域。指令被分类为在区域之间共享的收敛或发散和不同的存储器引用。插入线程循环以确保在通用CPU执行期间在不同线程之间正确共享内存。

8. 发明授权

US10152312B2 Dynamic compiler parallelism techniques 有权
公开(公告)号：US10152312B2
公开(公告)日：2018-12-11
申请号：US14602258
申请日：2015-01-21
申请人： Vinod Grover , Thibaut Lutz
发明人： Vinod Grover , Thibaut Lutz
IPC分类号： G06F8/41 , G06F9/455
摘要： Compiler techniques for inline parallelism and re-targetable parallel runtime execution of logic iterators enables selection thereof from the source code or dynamically during the object code execution.

9. 发明申请

US20160011857A1 Dynamic Compiler Parallelism Techniques 审中-公开
标题翻译：动态编译器并行技术
公开(公告)号：US20160011857A1
公开(公告)日：2016-01-14
申请号：US14602258
申请日：2015-01-21
申请人： Vinod Grover , Thibaut Lutz
发明人： Vinod Grover , Thibaut Lutz
IPC分类号： G06F9/45
CPC分类号： G06F8/4443 , G06F8/47 , G06F9/4552
摘要： Compiler techniques for inline parallelism and re-targetable parallel runtime execution of logic iterators enables selection thereof from the source code or dynamically during the object code execution.
摘要翻译：用于内联并行性和逻辑迭代器的可重定向并行运行时执行的编译器技术使得能够在源代码中进行选择，或者在目标代码执行期间动态地进行选择。

10. 发明授权

US08612732B2 Retargetting an application program for execution by a general purpose processor 有权
标题翻译：重新定位应用程序以供通用处理器执行
公开(公告)号：US08612732B2
公开(公告)日：2013-12-17
申请号：US12407711
申请日：2009-03-19
申请人： Vinod Grover , Bastiaan Joannes Matheus Aarts , Michael Murphy , Boris Beylin , Jayant B. Kolhe , Douglas Saylor
发明人： Vinod Grover , Bastiaan Joannes Matheus Aarts , Michael Murphy , Boris Beylin , Jayant B. Kolhe , Douglas Saylor
IPC分类号： G06F9/38
CPC分类号： G06F9/45537 , G06F8/45 , G06F8/456 , G06F9/4843 , G06F11/261 , G06F12/0253
摘要： One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU.
摘要翻译：本发明的一个实施例提出了一种用于翻译使用并行编程模型编写的应用程序的技术，用于在多核图形处理单元（GPU）上执行以由通用中央处理单元（CPU）执行。依赖于多核GPU的特定功能的应用程序的部分由翻译器转换，以供通用CPU执行。应用程序被划分为独立于同步的指令的区域。指令被分类为在区域之间共享的收敛或发散和不同的存储器引用。插入线程循环以确保在通用CPU执行期间在不同线程之间正确共享内存。

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