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1. 发明申请

US20170185404A1 Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processor 有权
公开(公告)号：US20170185404A1
公开(公告)日：2017-06-29
申请号：US14998299
申请日：2015-12-26
申请人： Vineeth Mekkat , Oleg Margulis , Jason M. Agron , Ethan Schuchman , Sebastian Winkel , Youfeng Wu , Gisle Dankel
发明人： Vineeth Mekkat , Oleg Margulis , Jason M. Agron , Ethan Schuchman , Sebastian Winkel , Youfeng Wu , Gisle Dankel
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/3826 , G06F9/3834 , G06F9/3838 , G06F9/3865
摘要： Embodiments of apparatus and methods for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.

2. 发明申请

US20160267009A1 METHOD AND APPARATUS FOR MEMORY ALIASING DETECTION IN AN OUT-OF-ORDER INSTRUCTION EXECUTION PLATFORM 有权
标题翻译：用于外部指令执行平台内存存储器检测的方法和装置
公开(公告)号：US20160267009A1
公开(公告)日：2016-09-15
申请号：US14643354
申请日：2015-03-10
申请人： Oleg Margulis , Sumit Ahuja , Polychronis Xekalakis , Yongjun Park , Vineeth Mekkat , Igor Yanover , Sebastian Winkel , Ethan Schuchman
发明人： Oleg Margulis , Sumit Ahuja , Polychronis Xekalakis , Yongjun Park , Vineeth Mekkat , Igor Yanover , Sebastian Winkel , Ethan Schuchman
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F9/38 , G06F9/3834 , G06F9/3838 , G06F9/3855 , G06F9/467 , G06F2212/1008 , G06F2212/452
摘要： A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and write operations in a program order and to responsively reorder the read and write operations; adjustment information attachment logic to associate adjustment information with one or more of the set of read and write operations, wherein for a read operation the adjustment information is to indicate a number of write operations which the read operation has bypassed and for a write operation the adjustment information is to indicate a number of read operations which have bypassed the write operation; and out-of-order processing logic to determine whether execution of the reordered read and write operations will result in a conflict based, at least in part, on the adjustment information associated with the one or more reads and writes.
摘要翻译：描述了用于别名检测的处理器和方法。例如，设备的一个实施例包括：重新排序逻辑以按照程序顺序接收一组读取和写入操作，并响应于重新排序读取和写入操作; 调整信息附加逻辑，用于将调整信息与所述一组读取和写入操作中的一个或多个相关联，其中对于读取操作，所述调整信息用于指示所述读取操作已绕过的写入操作的数量，并且对于写入操作，所述调整信息是指示绕过了写入操作的多个读取操作; 以及无序处理逻辑，以确定重新排序的读取和写入操作的执行是否将导致至少部分地基于与所述一个或多个读取和写入相关联的调整信息的冲突。

3. 发明申请

US20100169581A1 EXTENDING CACHE COHERENCY PROTOCOLS TO SUPPORT LOCALLY BUFFERED DATA 有权
标题翻译：扩展缓存协议来支持本地缓存数据
公开(公告)号：US20100169581A1
公开(公告)日：2010-07-01
申请号：US12346543
申请日：2008-12-30
申请人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Raanan Sade , Ehud Cohen , Oleg Margulis
发明人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Raanan Sade , Ehud Cohen , Oleg Margulis
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F9/3834 , G06F9/467 , G06F12/0831 , G06F12/084
摘要： A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffered manner. Here, the coherency state associated with cache lines to hold the data item are transitioned to a buffered state. In response to local requests for the buffered data item, the data item is provided to ensure internal transactional sequential ordering. However, in response to external access requests, a miss response is provided to ensure the transactionally updated data item is not made globally visible until commit. Upon commit, the buffered lines are transitioned to a modified state to make the data item globally visible.
摘要翻译：这里描述了用于扩展高速缓存一致性以保存缓冲数据以支持事务执行的方法和装置。以缓冲的方式执行引用与数据项相关联的地址的事务存储操作。这里，与保存数据项的高速缓存行相关联的一致性状态被转换到缓冲状态。响应缓冲数据项的本地请求，提供数据项以确保内部事务顺序排序。然而，响应于外部访问请求，提供了错误响应以确保事务更新的数据项在提交之前不会被全局可见。一旦提交，缓存的行将转换到修改状态，使数据项全局可见。

4. 发明授权

US08688917B2 Read and write monitoring attributes in transactional memory (TM) systems 有权
公开(公告)号：US08688917B2
公开(公告)日：2014-04-01
申请号：US13355302
申请日：2012-01-20
申请人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Raanan Sade , Ehud Cohen , Oleg Margulis
发明人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Raanan Sade , Ehud Cohen , Oleg Margulis
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/084
摘要： A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item.

5. 发明授权

US09001138B2 2-D gather instruction and a 2-D cache 有权
标题翻译： 2-D收集指令和2-D缓存
公开(公告)号：US09001138B2
公开(公告)日：2015-04-07
申请号：US13220402
申请日：2011-08-29
申请人： Boris Ginzburg , Oleg Margulis
发明人： Boris Ginzburg , Oleg Margulis
IPC分类号： G09G5/36 , G06T1/60 , G06F12/08
CPC分类号： G06F12/0875 , G06F2212/452 , G06T1/60
摘要： A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor. The two-dimensional (2-D) cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a two-dimensional structure of the 2-D image.
摘要翻译：处理器可以支持二维（2-D）采集指令和2-D缓存。处理器可以执行2-D收集指令以从存储在耦合到处理器的存储器中的二维（2-D）图像访问数据的一个或多个子块。二维（2-D）高速缓存可以将数据子块存储在多个高速缓存行中。此外，2-D缓存可以支持多个缓存行的访问，同时保留二维图像的二维结构。

6. 发明授权

US08352683B2 Method and system to reduce the power consumption of a memory device 有权
标题翻译：降低存储器件功耗的方法和系统
公开(公告)号：US08352683B2
公开(公告)日：2013-01-08
申请号：US12823047
申请日：2010-06-24
申请人： Ehud Cohen , Oleg Margulis , Raanan Sade , Stanislav Shwartsman
发明人： Ehud Cohen , Oleg Margulis , Raanan Sade , Stanislav Shwartsman
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F1/00
CPC分类号： G06F12/0864 , G06F12/0859 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is logic coupled with the data cache memory to facilitate access to only part of the N-ways of the N-way set-associative L1 cache memory in response to a load instruction or a store instruction. By reducing the number of ways to access the N-way set-associative L1 cache memory for each load or store request, the power requirements of the N-way set-associative L1 cache memory is reduced in one embodiment of the invention. In one embodiment of the invention, when a prediction is made that the accesses to cache memory only requires the data arrays of the N-way set-associative L1 cache memory, the access to the fill buffers are deactivated or disabled.
摘要翻译：一种降低存储器件功耗的方法和系统。在本发明的一个实施例中，存储器件是N路组合关联级（L1）高速缓冲存储器，并且存在与数据高速缓冲存储器耦合的逻辑，以便于仅访问N- 响应于加载指令或存储指令，单向设置关联L1高速缓冲存储器。通过减少针对每个加载或存储请求访问N路组合关联的L1高速缓冲存储器的方法的数量，在本发明的一个实施例中，减少了N路组合关联的L1高速缓冲存储器的功率需求。在本发明的一个实施例中，当预测到对高速缓存存储器的访问仅需要N路组关联的L1高速缓冲存储器的数据阵列时，对填充缓冲器的访问被去激活或禁用。

7. 发明申请

US20220100909A1 METHOD OF SECURING DEVICES USED IN THE INTERNET OF THINGS 有权
公开(公告)号：US20220100909A1
公开(公告)日：2022-03-31
申请号：US17518611
申请日：2021-11-04
申请人： Iurii V Iuzifovich , Oleg Margulis , Iurii I. Iuzifovich
发明人： Iurii V Iuzifovich , Oleg Margulis , Iurii I. Iuzifovich
IPC分类号： G06F21/76 , G06F1/16 , G06F15/78
摘要： Secure IoT devices and methods of use are disclosed herein. An example Internet-of-Things (IoT) device includes an interface for transmitting and receiving data on a network; and a chip comprising a reconfigurable hardware core configured to transmit the data using the interface. The reconfigurable hardware core is not vulnerable to malicious attacks can be used to replace a central processing unit (CPU) which is vulnerable to malicious attacks.

8. 发明申请

US20190278950A1 METHOD OF SECURING DEVICES USED IN THE INTERNET OF THINGS 审中-公开
公开(公告)号：US20190278950A1
公开(公告)日：2019-09-12
申请号：US15914905
申请日：2018-03-07
申请人： Iurii V. Iuzifovich , Oleg Margulis , Iurii I. Iuzifovich
发明人： Iurii V. Iuzifovich , Oleg Margulis , Iurii I. Iuzifovich
IPC分类号： G06F21/76 , G06F15/78 , G06F1/16
摘要： Secure IoT devices and methods of use are disclosed herein. An example Internet-of-Things (IoT) device includes an interface for transmitting and receiving data on a network; and a chip comprising a reconfigurable hardware core configured to transmit the data using the interface. The reconfigurable hardware core is not vulnerable to malicious attacks can be used to replace a central processing unit (CPU) which is vulnerable to malicious attacks.

9. 发明申请

US20150178217A1 2-D Gather Instruction and a 2-D Cache 审中-公开
标题翻译： 2-D收集指令和2-D缓存
公开(公告)号：US20150178217A1
公开(公告)日：2015-06-25
申请号：US14635403
申请日：2015-03-02
申请人： Boris Ginzburg , Oleg Margulis
发明人： Boris Ginzburg , Oleg Margulis
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F2212/452 , G06T1/60
摘要： A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a 2-D image stored in a memory coupled to the processor. The 2-D cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a 2-D structure of the 2-D image.
摘要翻译：处理器可以支持二维（2-D）采集指令和2-D缓存。处理器可以执行2-D收集指令以从存储在耦合到处理器的存储器中的2-D图像访问一个或多个数据子块。 2-D缓存可以将数据子块存储在多个高速缓存行中。此外，2-D高速缓存可以支持访问多于一条的高速缓存行，同时保留二维图像的二维结构。

10. 发明授权

US08769212B2 Memory model for hardware attributes within a transactional memory system 有权
标题翻译：事务内存系统中硬件属性的内存模型
公开(公告)号：US08769212B2
公开(公告)日：2014-07-01
申请号：US13359238
申请日：2012-01-26
申请人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
发明人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin , Ehud Cohen , Oleg Margulis
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/3838 , G06F11/0715 , G06F11/0724 , G06F11/073 , G06F11/0751 , G06F11/3017 , G06F11/3037 , G06F11/3089 , G06F11/3471 , G06F12/0831 , G06F12/084 , G06F2201/885
摘要： A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.
摘要翻译：这里描述了一种用于提供用于硬件属性以支持事务执行的存储器模型的方法和装置。在遇到诸如加载读取监视器，写入监视器或缓冲属性的测试监视器操作的硬件属性的负载时，响应于指示硬件属性已经丢失的丢失字段而发出故障。此外，基于地址依赖性和访问类型依赖性，为属性访问操作提供依赖操作，例如阻塞和转发。因此，在存储器模型中允许和限制属性丢失和测试的不同场景。

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