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1. 发明授权

US08339299B2 2-phase gain calibration and scaling scheme for switched capacitor sigma-delta modulator using a chopper voltage reference 有权
标题翻译：使用斩波电压参考的开关电容Σ-Δ调制器的2相增益校准和缩放方案
公开(公告)号：US08339299B2
公开(公告)日：2012-12-25
申请号：US13004127
申请日：2011-01-11
申请人： Vincent Quiquempoix , Yann Johner , Gabriele Bellini
发明人： Vincent Quiquempoix , Yann Johner , Gabriele Bellini
IPC分类号： H03M3/00
CPC分类号： H03M1/0663 , H03M1/0665 , H03M3/422 , H03M3/456 , H03M3/464
摘要： A sigma-delta modulator has a chopper voltage reference providing a reference signal having a clock dependent offset voltage, a single-bit or a multi-bit digital-to-analog converter (DAC); a plurality of capacitor pairs; a plurality of switches to couple any capacitor pair to an input or reference signal; and a control unit controlling sampling through said switches to perform a charge transfer in two phases wherein any capacitor pair can be selected to be assigned to the input or reference signal, wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically, and wherein a DAC output value and a reference offset state define switching sequences wherein each switching sequence independently rotates said capacitor pairs and wherein at least one switching sequence is selected depending on a current DAC output value and a current reference offset state.
摘要翻译： Σ-Δ调制器具有提供具有时钟相关偏移电压的参考信号的斩波器参考电压，单位或多位数模转换器（DAC）; 多个电容器对; 多个开关，用于将任何电容器对耦合到输入或参考信号; 以及控制单元，其控制通过所述开关的采样以执行两个阶段的电荷转移，其中可以选择任何电容器对来分配给输入或参考信号，其中在多个电荷传输之后，通过旋转增益误差来执行增益误差消除电容器对，并且其中DAC输出值和参考偏移状态定义切换序列，其中每个切换序列独立地旋转所述电容器对，并且其中根据当前DAC输出值和当前参考偏移状态来选择至少一个切换序列。

2. 发明申请

US20110163901A1 2-PHASE GAIN CALIBRATION AND SCALING SCHEME FOR SWITCHED CAPACITOR SIGMA-DELTA MODULATOR USING A CHOPPER VOLTAGE REFERENCE 有权
标题翻译：使用斩波电压参考的开关电容器SIGMA-DELTA调制器的2相增益校准和调整方案
公开(公告)号：US20110163901A1
公开(公告)日：2011-07-07
申请号：US13004127
申请日：2011-01-11
申请人： Vincent Quiquempoix , Yann Johner , Gabriele Bellini
发明人： Vincent Quiquempoix , Yann Johner , Gabriele Bellini
IPC分类号： H03M3/02
CPC分类号： H03M1/0663 , H03M1/0665 , H03M3/422 , H03M3/456 , H03M3/464
摘要： A sigma-delta modulator has a chopper voltage reference providing a reference signal having a clock dependent offset voltage, a single-bit or a multi-bit digital-to-analog converter (DAC); a plurality of capacitor pairs; a plurality of switches to couple any capacitor pair to an input or reference signal; and a control unit controlling sampling through said switches to perform a charge transfer in two phases wherein any capacitor pair can be selected to be assigned to the input or reference signal, wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically, and wherein a DAC output value and a reference offset state define switching sequences wherein each switching sequence independently rotates said capacitor pairs and wherein at least one switching sequence is selected depending on a current DAC output value and a current reference offset state.
摘要翻译： Σ-Δ调制器具有提供具有时钟相关偏移电压的参考信号的斩波器参考电压，单位或多位数模转换器（DAC）; 多个电容器对; 多个开关，用于将任何电容器对耦合到输入或参考信号; 以及控制单元，其控制通过所述开关的采样以执行两个阶段的电荷转移，其中可以选择任何电容器对来分配给输入或参考信号，其中在多个电荷传输之后，通过旋转增益误差来执行增益误差消除电容器对，并且其中DAC输出值和参考偏移状态定义切换序列，其中每个切换序列独立地旋转所述电容器对，并且其中根据当前DAC输出值和当前参考偏移状态来选择至少一个切换序列。

3. 发明申请

US20090031048A1 Configuring Multi-Bit Slave Addressing on a Serial Bus Using a Single External Connection 有权
标题翻译：使用单个外部连接在串行总线上配置多位从站寻址
公开(公告)号：US20090031048A1
公开(公告)日：2009-01-29
申请号：US12098725
申请日：2008-04-07
申请人： Patrick K. Richards , Vincent Quiquempoix , Gabriele Bellini
发明人： Patrick K. Richards , Vincent Quiquempoix , Gabriele Bellini
IPC分类号： G06F13/20
CPC分类号： G06F13/4072
摘要： Unique addresses for a plurality of devices may be programmed through a single external connection (pin) on each device by using a one of a plurality of different analog voltage or current values on the single external pin in combination with a serial clock of a serial data bus for each device requiring a unique binary address. The unique binary address is stored in the device after detection of certain number of clocks on the serial data bus. Once the unique binary address has been stored in the device, the single external connection may be used for another purpose such as a multifunction external connection. This unique binary address may be retained by the device until a power-on-reset (POR) or general reset condition occurs. Address detection and address load commands on the serial bus may also perform the same address definition and storage functions.
摘要翻译：可以通过在单个外部引脚上的多个不同的模拟电压或电流值中的一个结合串行数据的串行时钟来通过单个外部连接（引脚）来编程多个设备的唯一地址每个设备的总线需要一个唯一的二进制地址。在串行数据总线上检测到一定数量的时钟之后，唯一的二进制地址存储在设备中。一旦唯一的二进制地址已经存储在设备中，单个外部连接可以用于另一目的，例如多功能外部连接。该唯一的二进制地址可能被器件保留，直到出现上电复位（POR）或一般复位条件。串行总线上的地址检测和地址加载命令也可以执行相同的地址定义和存储功能。

4. 发明授权

US06788233B1 Digital decimation filter 有权
标题翻译：数字抽取滤波器
公开(公告)号：US06788233B1
公开(公告)日：2004-09-07
申请号：US10642420
申请日：2003-08-15
申请人： Vincent Quiquempoix , Gabriele Bellini , Jerry Collings
发明人： Vincent Quiquempoix , Gabriele Bellini , Jerry Collings
IPC分类号： H03M300
CPC分类号： H03H17/0664 , H03H17/025 , H03H17/0283 , H03H17/0294
摘要： A digital decimation filter with programmable frequency notches is disclosed. The digital decimation filter performs integration, differentiation, and scaling to produce a filtered output signal. The differentiation is preformed by a programmable counter. The filter has a control unit that controls the behavior of the filter. The control unit has registers to contain ther values of the frequency notches of the filter. The control unit activates the differentiator based on the value of the frequency notches in order to achieve filtration. The scaling unit uses a register, a bit shifter, and an adder to minimize complexity. The digital decimation filter provides high rejection with low complexity.
摘要翻译：公开了一种具有可编程频率切口的数字抽取滤波器。数字抽取滤波器执行积分，微分和缩放以产生滤波的输出信号。微分是由可编程计数器执行的。过滤器具有控制单元，用于控制过滤器的行为。控制单元具有寄存器以包含滤波器的频率缺口的值。控制单元基于频率凹口的值激活微分器以实现过滤。缩放单元使用寄存器，位移器和加法器来最小化复杂度。数字抽取滤波器具有低复杂度的高抑制。

5. 发明授权

US07962662B2 Configuring multi-bit slave addressing on a serial bus using a single external connection 有权
标题翻译：使用单个外部连接在串行总线上配置多位从站寻址
公开(公告)号：US07962662B2
公开(公告)日：2011-06-14
申请号：US12894296
申请日：2010-09-30
申请人： Patrick K. Richards , Vincent Quiquempoix , Gabriele Bellini
发明人： Patrick K. Richards , Vincent Quiquempoix , Gabriele Bellini
IPC分类号： G06F3/00 , G06F13/12
CPC分类号： G06F13/4072
摘要： Unique addresses for a plurality of devices may be programmed through a single external connection (pin) on each device by using a one of a plurality of different analog voltage or current values on the single external pin in combination with a serial clock of a serial data bus for each device requiring a unique binary address. The unique binary address is stored in the device after detection of certain number of clocks on the serial data bus. Once the unique binary address has been stored in the device, the single external connection may be used for another purpose such as a multifunction external connection. This unique binary address may be retained by the device until a power-on-reset (POR) or general reset condition occurs. Address detection and address load commands on the serial bus may also perform the same address definition and storage functions.
摘要翻译：可以通过在单个外部引脚上的多个不同的模拟电压或电流值中的一个结合串行数据的串行时钟来通过单个外部连接（引脚）来编程多个设备的唯一地址每个设备的总线需要一个唯一的二进制地址。在串行数据总线上检测到一定数量的时钟之后，唯一的二进制地址存储在设备中。一旦唯一的二进制地址已经存储在设备中，单个外部连接可以用于另一目的，例如多功能外部连接。该唯一的二进制地址可能被器件保留，直到出现上电复位（POR）或一般复位条件。串行总线上的地址检测和地址加载命令也可以执行相同的地址定义和存储功能。

6. 发明授权

US07827330B2 Configuring multi-bit slave addressing on a serial bus using a single external connection 有权
标题翻译：使用单个外部连接在串行总线上配置多位从站寻址
公开(公告)号：US07827330B2
公开(公告)日：2010-11-02
申请号：US12098725
申请日：2008-04-07
申请人： Patrick K. Richards , Vincent Quiquempoix , Gabriele Bellini
发明人： Patrick K. Richards , Vincent Quiquempoix , Gabriele Bellini
IPC分类号： G06F13/12 , G06F3/00
CPC分类号： G06F13/4072
摘要： Unique addresses for a plurality of devices may be programmed through a single external connection (pin) on each device by using a one of a plurality of different analog voltage or current values on the single external pin in combination with a serial clock of a serial data bus for each device requiring a unique binary address. The unique binary address is stored in the device after detection of certain number of clocks on the serial data bus. Once the unique binary address has been stored in the device, the single external connection may be used for another purpose such as a multifunction external connection. This unique binary address may be retained by the device until a power-on-reset (POR) or general reset condition occurs. Address detection and address load commands on the serial bus may also perform the same address definition and storage functions.
摘要翻译：可以通过在单个外部引脚上的多个不同的模拟电压或电流值中的一个结合串行数据的串行时钟来通过单个外部连接（引脚）来编程多个设备的唯一地址每个设备的总线需要一个唯一的二进制地址。在串行数据总线上检测到一定数量的时钟之后，唯一的二进制地址存储在设备中。一旦唯一的二进制地址已经存储在设备中，单个外部连接可以用于另一目的，例如多功能外部连接。该唯一的二进制地址可能被器件保留，直到出现上电复位（POR）或一般复位条件。串行总线上的地址检测和地址加载命令也可以执行相同的地址定义和存储功能。

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