专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06849940B1 Integrated circuit package for the transfer of heat generated by the inte circuit and method of fabricating same 有权
标题翻译：用于传输由积分电路产生的热的集成电路封装及其制造方法
公开(公告)号：US06849940B1
公开(公告)日：2005-02-01
申请号：US09716734
申请日：2000-11-20
申请人： Vincent K. Chan , Samuel W. Ho
发明人： Vincent K. Chan , Samuel W. Ho
IPC分类号： H01L23/16 , H01L23/31 , H01L23/433 , H01L25/065 , H01L23/28 , H01L23/10 , H01L23/22 , H05K7/20
CPC分类号： H01L23/16 , H01L23/3128 , H01L23/433 , H01L23/4334 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L2224/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01019 , H01L2924/07802 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package includes a first or active substrate and a second or passive substrate. The active substrate includes at least one circuit that generates heat during circuit operation. The passive substrate does not include any heat-generating circuits, although the passive substrate may include passive, disabled or dormant circuitry. The two substrates are preferably fabricated of semiconductor material and have substantially equal coefficients of thermal expansion. The passive substrate is thermally coupled to the active substrate preferably using a thin layer of adhesive, such as an epoxy. The passive substrate serves to thermally conduct the heat generated by the circuits of the active substrate away from the active substrate. An internal metallic heat sink may be optionally thermally coupled to the passive substrate to further aid in the transfer of heat away from the active substrate.
摘要翻译：集成电路封装包括第一或有源衬底和第二或无源衬底。有源衬底包括在电路操作期间产生热量的至少一个电路。无源基板不包括任何发热电路，尽管无源基板可包括无源，禁用或休眠电路。两个基板优选由半导体材料制成并且具有基本上相等的热膨胀系数。被动衬底优选地使用诸如环氧树脂的粘合剂薄层热耦合到有源衬底。被动衬底用于将由活性衬底的电路产生的热量热传导远离有源衬底。内部金属散热器可以可选地热耦合到无源基板，以进一步有助于将热量从活性基板传递。

2. 发明申请

US20080197477A1 Flip-Chip Grid Ball Array Strip and Package 有权
标题翻译：倒装芯片网格阵列条和封装
公开(公告)号：US20080197477A1
公开(公告)日：2008-08-21
申请号：US12110798
申请日：2008-04-28
申请人： Neil R. McLellan , Vincent K. Chan , Roden R. Topacio
发明人： Neil R. McLellan , Vincent K. Chan , Roden R. Topacio
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L21/563 , H01L21/561 , H01L23/16 , H01L23/24 , H01L23/3128 , H01L24/97 , H01L2224/16225 , H01L2224/26175 , H01L2224/27013 , H01L2224/32225 , H01L2224/73204 , H01L2224/83051 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units. The use of a retention wall of a stiffener layer over an expensive substrate layer allows for the use of disposable edges around the strip including indexing holes or other holding mechanisms. What is also contemplated is a method of manufacture of a compact strip, matrix, or array comprised of a plurality of integrated circuit packages where no waste or additional cuts are needed to produce individual integrated circuit packages.
摘要翻译：本公开涉及一种改进的集成电路封装，其具有邻近衬底上的封装集成芯片定位的密封剂保留结构。该结构允许在封装的集成芯片下放置和保留更大量的密封剂渗入。放置在基板上的保持壁交替地用作能够保持机械性能以与更理想的较薄基板一起使用的基板加强件。在一个实施例中，使用集成电路封装的加强层中的开口和凹槽容纳无源电子部件，以在使用更薄的衬底时保持机械特性。使用保留壁或加强件允许使用条带，矩阵或阵列技术来制造这些集成电路封装，其中具有多个集成电路封装的较大的板在工业上被制造然后切割成各个单元。在昂贵的基底层上使用加强层的保持壁允许使用围绕条带的一次性边缘，包括分度孔或其它保持机构。还可以想到的是制造由多个集成电路封装组成的紧凑型条，矩阵或阵列的方法，其中不需要浪费或额外的切割来产生单独的集成电路封装。

3. 发明申请

US20080054490A1 Flip-Chip Ball Grid Array Strip and Package 审中-公开
标题翻译：倒装芯片球栅阵列条和封装
公开(公告)号：US20080054490A1
公开(公告)日：2008-03-06
申请号：US11469194
申请日：2006-08-31
申请人： Neil R. McLellan , Vincent K. Chan , Roden R. Topacio
发明人： Neil R. McLellan , Vincent K. Chan , Roden R. Topacio
IPC分类号： H01L23/48 , H01L21/00
CPC分类号： H01L21/563 , H01L21/561 , H01L23/16 , H01L23/24 , H01L23/3128 , H01L24/97 , H01L2224/16225 , H01L2224/26175 , H01L2224/27013 , H01L2224/32225 , H01L2224/73204 , H01L2224/83051 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units. The use of a retention wall of a stiffener layer over an expensive substrate layer allows for the use of disposable edges around the strip including indexing holes or other holding mechanisms. What is also contemplated is a method of manufacture of a compact strip, matrix, or array comprised of a plurality of integrated circuit packages where no waste or additional cuts are needed to produce individual integrated circuit packages.
摘要翻译：本公开涉及一种改进的集成电路封装，其具有邻近衬底上的封装集成芯片定位的密封剂保留结构。该结构允许在封装的集成芯片下放置和保留更大量的密封剂渗入。放置在基板上的保持壁交替地用作能够保持机械性能以与更理想的较薄基板一起使用的基板加强件。在一个实施例中，使用集成电路封装的加强层中的开口和凹槽容纳无源电子部件，以在使用更薄的衬底时保持机械特性。使用保留壁或加强件允许使用条带，矩阵或阵列技术来制造这些集成电路封装，其中具有多个集成电路封装的较大的板在工业上被制造然后切割成各个单元。在昂贵的基底层上使用加强层的保持壁允许使用围绕条带的一次性边缘，包括分度孔或其它保持机构。还可以想到的是制造由多个集成电路封装组成的紧凑型条，矩阵或阵列的方法，其中不需要浪费或额外的切割来产生单独的集成电路封装。

4. 发明授权

US07015826B1 Method and apparatus for sensing and transmitting a body characteristic of a host 有权
标题翻译：用于感测和传送主体特征的方法和装置
公开(公告)号：US07015826B1
公开(公告)日：2006-03-21
申请号：US10114875
申请日：2002-04-02
申请人： Vincent K. Chan , Ezequiel Mejia
发明人： Vincent K. Chan , Ezequiel Mejia
IPC分类号： G08C17/00
CPC分类号： A01K11/006 , A01K29/00 , G01K1/024 , G01K7/015 , G06K19/0717 , G06K19/0723 , H04Q9/00 , H04Q2209/47 , H04Q2209/75
摘要： A passive transponder including an integrated sensor is disclosed. The transponder receives an interrogation signal from a scanner, and is operable to transmit identification information and body characteristic information to a scanner. The scanner is operable to receive the identification and body characteristic information and display and/or store the information. The sensor is integrated into the transponder. If temperature is to be sensed, the transponder determines the temperature of the host using the temperature dependent characteristics of the P-N junction of the integrated circuit.
摘要翻译：公开了一种包括集成传感器的无源应答器。应答器从扫描器接收询问信号，并且可操作以将识别信息和身体特征信息发送到扫描器。扫描器可操作以接收识别和身体特征信息，并显示和/或存储信息。传感器集成到应答器中。如果要感测温度，应答器使用集成电路的P-N结的温度依赖特性来确定主机的温度。

5. 发明授权

US06798667B2 Solder ball collapse control apparatus and method thereof 有权
标题翻译：焊球塌陷控制装置及其方法
公开(公告)号：US06798667B2
公开(公告)日：2004-09-28
申请号：US10064857
申请日：2002-08-23
申请人： Vincent K. Chan
发明人： Vincent K. Chan
IPC分类号： H05K710
CPC分类号： B23K1/0016 , H01L23/49816 , H01L2924/0002 , H05K3/3436 , H05K3/3463 , H05K2201/094 , H05K2201/2036 , Y02P70/613 , H01L2924/00
摘要： A solder ball collapse control apparatus and method thereof includes a plurality of first solder members, pieces of solder material in a shape capable of being used to properly create a solder joint. The first solder members have a first solder dimension and a first melting temperature and are disposed on a carrier substrate, wherein the first solder members include any piece of material capable of being disposed using a solder dispensing machine. The apparatus and method further includes a plurality of second members having a second dimension and a second melting temperature, disposed on the carrier substrate in relation to the plurality of first solder members. The second members include any piece of material capable of being disposed using the solder dispensing machine, wherein the first solder member dimension is greater than the second member dimension and the second melting temperature is greater than the first melting temperature.
摘要翻译：焊球塌陷控制装置及其方法包括多个第一焊料构件，能够用于适当地形成焊点的形状的焊料材料片。第一焊料构件具有第一焊料尺寸和第一熔融温度并且设置在载体基板上，其中第一焊料构件包括能够使用焊料分配机布置的任何材料片。该装置和方法还包括多个具有第二尺寸和第二熔化温度的第二构件，其相对于多个第一焊料构件设置在载体衬底上。第二构件包括能够使用焊料分配机布置的任何一种材料，其中第一焊料构件尺寸大于第二构件尺寸，并且第二熔化温度大于第一熔化温度。

6. 发明授权

US08847383B2 Integrated circuit package strip with stiffener 有权
标题翻译：带加强筋的集成电路封装带
公开(公告)号：US08847383B2
公开(公告)日：2014-09-30
申请号：US13363620
申请日：2012-02-01
申请人： Neil R. McLellan , Vincent K. Chan , Roden R. Topacio, III
发明人： Neil R. McLellan , Vincent K. Chan , Roden R. Topacio, III
IPC分类号： H01L23/48 , H01L21/56 , H01L23/16 , H01L23/00 , H01L23/24 , H01L23/31
CPC分类号： H01L21/563 , H01L21/561 , H01L23/16 , H01L23/24 , H01L23/3128 , H01L24/97 , H01L2224/16225 , H01L2224/26175 , H01L2224/27013 , H01L2224/32225 , H01L2224/73204 , H01L2224/83051 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： An integrated circuit package strip employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.
摘要翻译：集成电路封装带采用加强层，该加强层容纳无源电子部件以在使用更薄的衬底时保持机械性能。使用保留壁或加强件允许使用条带，矩阵或阵列技术来制造这些集成电路封装，其中具有多个集成电路封装的较大的板在工业上被制造然后切割成各个单元。

7. 发明授权

US07985621B2 Method and apparatus for making semiconductor packages 有权
标题翻译：制造半导体封装的方法和装置
公开(公告)号：US07985621B2
公开(公告)日：2011-07-26
申请号：US11469256
申请日：2006-08-31
申请人： Vincent K. Chan , Neil McLellan , Roden Topacio
发明人： Vincent K. Chan , Neil McLellan , Roden Topacio
IPC分类号： H01L21/00 , H01L23/34 , H01L23/48 , H01L23/52 , H01L23/40
CPC分类号： H01L21/563 , H01L21/6835 , H01L23/16 , H01L23/562 , H01L2221/68345 , H01L2224/73203 , H01L2924/09701 , H01L2924/19041 , H01L2924/351
摘要： A method of packaging a plurality of semiconductor chips comprises: providing a substrate panel having a first coefficient of thermal expansion (CTE); providing a carrier having a second CTE that is less than the first CTE; heating the substrate panel and the carrier to first and second elevated temperatures respectively; mounting the substrate panel at about the first elevated temperature to the carrier, the carrier being at said second elevated temperature, to provide a connection between the carrier and the substrate panel; and cooling the carrier and the substrate panel from the first and second elevated temperatures thereby putting the substrate panel into tension in at least one direction. A stiffener panel may be affixed to the substrate panel and heated to an elevated temperature and while the substrate panel is heated to an elevated temperature. A plurality of dies may be mounted and electrically connected to the substrate panel. Under-filling of the plurality of dies may occur with the stiffener panel affixed to the substrate panel.
摘要翻译：包装多个半导体芯片的方法包括：提供具有第一热膨胀系数（CTE）的基板; 提供具有小于所述第一CTE的第二CTE的载体; 将基板和载体分别加热到第一和第二升高温度; 将所述衬底面板在所述第一升高温度下安装到所述载体，所述载体处于所述第二升高温度，以提供所述载体和所述衬底面板之间的连接; 以及从所述第一和第二升高的温度冷却所述载体和所述基板，从而使所述基板在至少一个方向上处于张力状态。加强板可以固定到基板面板上并加热到升高的温度，同时将基板面板加热到升高的温度。可以将多个管芯安装并电连接到衬底面板。多个模具的欠填充可以在加强板固定到基板上的情况下发生。

8. 发明申请

US20080057625A1 METHOD AND APPARATUS FOR MAKING SEMICONDUCTOR PACKAGES 有权
标题翻译：制造半导体封装的方法和装置
公开(公告)号：US20080057625A1
公开(公告)日：2008-03-06
申请号：US11469256
申请日：2006-08-31
申请人： Vincent K. Chan , Neil McLellan , Roden Topacio
发明人： Vincent K. Chan , Neil McLellan , Roden Topacio
IPC分类号： H01L21/58
CPC分类号： H01L21/563 , H01L21/6835 , H01L23/16 , H01L23/562 , H01L2221/68345 , H01L2224/73203 , H01L2924/09701 , H01L2924/19041 , H01L2924/351
摘要： A method of packaging a plurality of semiconductor chips comprises: providing a substrate panel having a first coefficient of thermal expansion (CTE); providing a carrier having a second CTE that is less than the first CTE; heating the substrate panel and the carrier to first and second elevated temperatures respectively; mounting the substrate panel at about the first elevated temperature to the carrier, the carrier being at said second elevated temperature, to provide a connection between the carrier and the substrate panel; and cooling the carrier and the substrate panel from the first and second elevated temperatures thereby putting the substrate panel into tension in at least one direction. A stiffener panel may be affixed to the substrate panel and heated to an elevated temperature and while the substrate panel is heated to an elevated temperature. A plurality of dies may be mounted and electrically connected to the substrate panel. Under-filling of the plurality of dies may occur with the stiffener panel affixed to the substrate panel.
摘要翻译：包装多个半导体芯片的方法包括：提供具有第一热膨胀系数（CTE）的基板; 提供具有小于所述第一CTE的第二CTE的载体; 将基板和载体分别加热到第一和第二升高温度; 将所述衬底面板在所述第一升高温度下安装到所述载体，所述载体处于所述第二升高温度，以提供所述载体和所述衬底面板之间的连接; 以及从所述第一和第二升高的温度冷却所述载体和所述基板，从而使所述基板在至少一个方向上处于张力状态。加强板可以固定到基板面板上并加热到升高的温度，同时将基板面板加热到升高的温度。可以将多个管芯安装并电连接到衬底面板。多个模具的欠填充可以在加强板固定到基板上的情况下发生。

9. 发明授权

US08637391B2 Flip chip semiconductor assembly with variable volume solder bumps 有权
标题翻译：具有可变体积焊料凸块的倒装芯片半导体组件
公开(公告)号：US08637391B2
公开(公告)日：2014-01-28
申请号：US12437027
申请日：2009-05-07
申请人： Vincent K. Chan
发明人： Vincent K. Chan
IPC分类号： H01L21/44
CPC分类号： H01L21/563 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/28 , H01L24/81 , H01L2224/0401 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/0603 , H01L2224/1147 , H01L2224/13099 , H01L2224/13111 , H01L2224/14 , H01L2224/1403 , H01L2224/16225 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81121 , H01L2224/8121 , H01L2224/81815 , H01L2224/8191 , H01L2224/83102 , H01L2224/83855 , H01L2224/92125 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/0133 , H01L2924/014 , H01L2924/14 , H01L2924/157 , H01L2924/20106 , H01L2924/20107 , H01L2924/20108 , H01L2924/20109 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/0665
摘要： A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads.
摘要翻译：公开了一种制造半导体芯片的方法。具有多个管芯焊盘的管芯在包括多个衬底焊盘的半导体封装中附接到衬底。该方法包括形成从模片垫延伸的不同体积的导电柱凸起; 将每个柱状凸块连接到相应的衬底垫以形成子组件; 并且回流子组件，使得柱状突起在芯片焊盘和衬底焊盘之间形成坚固的电气和机械连接。

10. 发明申请

US20120127689A1 INTEGRATED PACKAGE CIRCUIT WITH STIFFENER 有权
标题翻译：集成封装电路与STIFFERER
公开(公告)号：US20120127689A1
公开(公告)日：2012-05-24
申请号：US13363620
申请日：2012-02-01
申请人： Neil R. McLellan , Vincent K. Chan , Roden R. Topacio
发明人： Neil R. McLellan , Vincent K. Chan , Roden R. Topacio
IPC分类号： H01L21/56 , H01L23/12
CPC分类号： H01L21/563 , H01L21/561 , H01L23/16 , H01L23/24 , H01L23/3128 , H01L24/97 , H01L2224/16225 , H01L2224/26175 , H01L2224/27013 , H01L2224/32225 , H01L2224/73204 , H01L2224/83051 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： The present disclosure relates to an improved integrated circuit package and method with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.
摘要翻译：本公开涉及一种改进的集成电路封装和方法，其具有邻近衬底上的封装集成芯片定位的密封剂保留结构。该结构允许在封装的集成芯片下放置和保留更大量的密封剂渗入。放置在基板上的保持壁交替地用作能够保持机械性能以与更理想的较薄基板一起使用的基板加强件。在一个实施例中，使用集成电路封装的加强层中的开口和凹槽容纳无源电子部件，以在使用更薄的衬底时保持机械特性。使用保留壁或加强件允许使用条带，矩阵或阵列技术来制造这些集成电路封装，其中具有多个集成电路封装的较大的板在工业上被制造然后切割成各个单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式