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1. 发明申请

US20110268163A1 RF DIGITAL SPUR REDUCTION 有权
标题翻译：射频数字减少
公开(公告)号：US20110268163A1
公开(公告)日：2011-11-03
申请号：US13096495
申请日：2011-04-28
申请人： Vincent Fillatre , Jean-Robert Tourret
发明人： Vincent Fillatre , Jean-Robert Tourret
IPC分类号： H04B1/40
CPC分类号： H04B15/06 , H04B2215/064 , H04B2215/065
摘要： Digital spur reduction in which spurs are kept outside selected channels of interest. An integrated radiofrequency transceiver circuit has digital and analogue components, the circuit includes a radiofrequency signal receiver having a local oscillator signal generator configured to provide a local oscillator signal at a frequency fLO and a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal; and a clock signal generator configured to generate a digital clock signal at a frequency fDIG for operation of the digital components, where the local oscillator signal and/or a reference signal from which the local oscillator signal is derived are generated such that digital spurs lie outside a band selected by the receiver.
摘要翻译：数字刺激减少，其中马刺保持在选定的感兴趣的渠道之外。集成射频收发器电路具有数字和模拟部件，该电路包括射频信号接收器，其具有本地振荡器信号发生器，该本地振荡器信号发生器被配置为以频率fLO提供本地振荡器信号，以及混频器，其被配置为将输入射频信号与本地振荡器信号以产生中频信号; 以及时钟信号发生器，被配置为产生频率为fDIG的数字时钟信号，用于数字分量的操作，其中产生本地振荡器信号和/或导出本地振荡器信号的参考信号，使得数字马刺位于外部由接收器选择的频带。

2. 发明授权

US08902953B2 RF digital spur reduction 有权
标题翻译：射频数字支线减少
公开(公告)号：US08902953B2
公开(公告)日：2014-12-02
申请号：US13096495
申请日：2011-04-28
申请人： Vincent Fillatre , Jean-Robert Tourret
发明人： Vincent Fillatre , Jean-Robert Tourret
IPC分类号： H04B1/38 , H04L5/16 , H04B15/06
CPC分类号： H04B15/06 , H04B2215/064 , H04B2215/065
摘要： Digital spur reduction in which spurs are kept outside selected channels of interest. An integrated radiofrequency transceiver circuit has digital and analogue components, the circuit includes a radiofrequency signal receiver having a local oscillator signal generator configured to provide a local oscillator signal at a frequency fLO and a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal; and a clock signal generator configured to generate a digital clock signal at a frequency fDIG for operation of the digital components, where the local oscillator signal and/or a reference signal from which the local oscillator signal is derived are generated such that digital spurs lie outside a band selected by the receiver.
摘要翻译：数字刺激减少，其中马刺保持在选定的感兴趣的渠道之外。集成射频收发器电路具有数字和模拟部件，该电路包括射频信号接收器，其具有本地振荡器信号发生器，该本地振荡器信号发生器被配置为以频率fLO提供本地振荡器信号，以及混频器，其被配置为将输入射频信号与本地振荡器信号以产生中频信号; 以及时钟信号发生器，被配置为产生频率为fDIG的数字时钟信号，用于数字分量的操作，其中产生本地振荡器信号和/或导出本地振荡器信号的参考信号，使得数字马刺位于外部由接收器选择的频带。

3. 发明授权

US08682273B2 RF digital spur reduction 有权
标题翻译：射频数字支线减少
公开(公告)号：US08682273B2
公开(公告)日：2014-03-25
申请号：US13096513
申请日：2011-04-28
申请人： Vincent Fillatre , Jean-Robert Tourret
发明人： Vincent Fillatre , Jean-Robert Tourret
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H04B15/04 , H04B1/30 , H04B2215/064
摘要： Digital spur reduction in which spurs are kept outside selected channels of interest, with illustrative embodiments relating to an integrated radiofrequency transceiver circuit having digital and analogue components, the circuit having a radiofrequency signal receiver with a local oscillator signal generator configured to provide a local oscillator signal at a frequency fLO and a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal; and a clock signal generator configured to generate a digital clock signal at a frequency fDIG for operation of the digital components, where the local oscillator signal and/or a reference signal from which the local oscillator signal is derived are generated such that digital spurs lie outside a band selected by the receiver.
摘要翻译：数字杂散减少，其中马刺保持在所选择的感兴趣的信道之外，具有涉及具有数字和模拟部件的集成射频收发器电路的说明性实施例，该电路具有射频信号接收机，本地振荡器信号发生器被配置为提供本地振荡器信号频率fLO和混频器，被配置为将输入射频信号与本地振荡器信号组合以产生中频信号; 以及时钟信号发生器，被配置为产生频率为fDIG的数字时钟信号，用于数字分量的操作，其中产生本地振荡器信号和/或导出本地振荡器信号的参考信号，使得数字马刺位于外部由接收器选择的频带。

4. 发明申请

US20110268164A1 RF DIGITAL SPUR REDUCTION 有权
标题翻译：射频数字减少
公开(公告)号：US20110268164A1
公开(公告)日：2011-11-03
申请号：US13096513
申请日：2011-04-28
申请人： Vincent Fillatre , Jean-Robert Tourret
发明人： Vincent Fillatre , Jean-Robert Tourret
IPC分类号： H04B1/38
CPC分类号： H04B15/04 , H04B1/30 , H04B2215/064
摘要： Digital spur reduction in which spurs are kept outside selected channels of interest, with illustrative embodiments relating to an integrated radiofrequency transceiver circuit having digital and analogue components, the circuit having a radiofrequency signal receiver with a local oscillator signal generator configured to provide a local oscillator signal at a frequency fLO and a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal; and a clock signal generator configured to generate a digital clock signal at a frequency fDIG for operation of the digital components, where the local oscillator signal and/or a reference signal from which the local oscillator signal is derived are generated such that digital spurs lie outside a band selected by the receiver.
摘要翻译：数字杂散减少，其中马刺保持在所选择的感兴趣的频道之外，具有涉及具有数字和模拟分量的集成射频收发器电路的说明性实施例，该电路具有射频信号接收机，其具有本地振荡器信号发生器，其被配置为提供本地振荡器信号频率fLO和混频器，被配置为将输入射频信号与本地振荡器信号组合以产生中频信号; 以及时钟信号发生器，被配置为产生频率为fDIG的数字时钟信号，用于数字分量的操作，其中产生本地振荡器信号和/或导出本地振荡器信号的参考信号，使得数字马刺位于外部由接收器选择的频带。

5. 发明授权

US08350597B2 Low voltage self calibrated CMOS peak detector 有权
标题翻译：低电压自校准CMOS峰值检测器
公开(公告)号：US08350597B2
公开(公告)日：2013-01-08
申请号：US13123844
申请日：2009-10-07
申请人： Jean-Robert Tourret
发明人： Jean-Robert Tourret
IPC分类号： H03K5/153
CPC分类号： H03K5/1532 , G01R19/04 , G01R35/005
摘要： The present invention relates to a low-voltage self-calibrated peak detector (100). Using a two-step calibration process that compensates the offset errors introduced by the respective first, second and third comparators (122, 128, 130), the peak detection is made accurate whatever temperature, process or mismatch spreads. Its input bandwidth can be as high as the bandwidth of an operational amplifier of unity gain. In a rail-to-rail configuration, it can be implemented into a fully differential low-voltage self-calibrated CMOS peak detector (200), which can have a very high conversion gain (α) and a very high input signal dynamic ranging.
摘要翻译：本发明涉及一种低电压自校准峰值检测器（100）。使用补偿由相应的第一，第二和第三比较器（122,128,130）引入的偏移误差的两步校准过程，无论温度，过程或不匹配扩散，峰值检测都是准确的。其输入带宽可以与运算放大器的单位增益的带宽一样高。在轨到轨配置中，它可以实现为全差分低电压自校准CMOS峰值检测器（200），其可以具有非常高的转换增益（α）和非常高的输入信号动态范围。

6. 发明申请

US20110241732A1 LOW VOLTAGE SELF CALIBRATED CMOS PEAK DETECTOR 有权
标题翻译：低电压自校准CMOS峰值检波器
公开(公告)号：US20110241732A1
公开(公告)日：2011-10-06
申请号：US13123844
申请日：2009-10-07
申请人： Jean-Robert Tourret
发明人： Jean-Robert Tourret
IPC分类号： H03K5/1532
CPC分类号： H03K5/1532 , G01R19/04 , G01R35/005
摘要： The present invention relates to a low-voltage self-calibrated peak detector (100). Using a two-step calibration process that compensates the offset errors introduced by the respective first, second and third comparators (122, 128, 130), the peak detection is made accurate whatever temperature, process or mismatch spreads. Its input bandwidth can be as high as the bandwidth of an operational amplifier of unity gain. In a rail-to-rail configuration, it can be implemented into a fully differential low-voltage self-calibrated CMOS peak detector (200), which can have a very high conversion gain (α) and a very high input signal dynamic ranging.
摘要翻译：本发明涉及一种低电压自校准峰值检测器（100）。使用补偿由相应的第一，第二和第三比较器（122,128,130）引入的偏移误差的两步校准过程，无论温度，过程或不匹配扩散，峰值检测都是准确的。其输入带宽可以与运算放大器的单位增益的带宽一样高。在轨到轨配置中，它可以实现为全差分低电压自校准CMOS峰值检测器（200），其可以具有非常高的转换增益（α）和非常高的输入信号动态范围。

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