专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07439988B1 Apparatus, system, and method for clipping graphics primitives with respect to a clipping plane 有权
标题翻译：相对于裁剪平面剪切图形基元的装置，系统和方法
公开(公告)号：US07439988B1
公开(公告)日：2008-10-21
申请号：US11295200
申请日：2005-12-05
申请人： Vimal S. Parikh , Henry Packard Moreton , Lordson L. Yue
发明人： Vimal S. Parikh , Henry Packard Moreton , Lordson L. Yue
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06T15/30
摘要： Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a clipping module includes a mapping unit and a clipping engine that is connected to the mapping unit. The mapping unit is configured to map a graphics primitive onto a canonical representation that is defined with respect to a clipping plane. The clipping engine is configured to clip the graphics primitive with respect to the clipping plane based on the canonical representation.
摘要翻译：描述用于剪切图形基元的装置，系统和方法。在一个实施例中，剪辑模块包括连接到映射单元的映射单元和剪辑引擎。映射单元被配置为将图形基元映射到相对于剪切平面定义的规范表示。剪辑引擎被配置为基于规范表示来相对于裁剪平面剪切图形原语。

2. 发明授权

US07542046B1 Programmable clipping engine for clipping graphics primitives 有权
标题翻译：可编程剪辑引擎，用于剪切图形原语
公开(公告)号：US07542046B1
公开(公告)日：2009-06-02
申请号：US11475599
申请日：2006-06-26
申请人： Lordson L. Yue , Vimal S. Parikh , Andrew J. Tao
发明人： Lordson L. Yue , Vimal S. Parikh , Andrew J. Tao
IPC分类号： G06F12/00
CPC分类号： G06T1/60
摘要： An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit, a read-only memory that is connected to the clipping unit, a read-write memory that is connected to the clipping unit, and an addressing unit that is connected to the read-only memory and the read-write memory. The read-only memory is configured to store a clipping program, and the read-write memory is configured to store a patch program. The addressing unit is configured to selectively address one of the read-only memory and the read-write memory based on a set of input conditions.
摘要翻译：描述用于剪切图形基元的装置，系统和方法。在一个实施例中，图形处理装置包括剪切单元，连接到剪切单元的只读存储器，连接到剪切单元的读写存储器，以及连接到读取存储器的寻址单元，只读存储器和读写存储器。只读存储器被配置为存储剪切程序，并且读写存储器被配置为存储补丁程序。寻址单元被配置为基于一组输入条件来选择性地寻址只读存储器和读写存储器中的一个。

3. 发明授权

US08432406B1 Apparatus, system, and method for clipping graphics primitives with accelerated context switching 有权
标题翻译：用于通过加速上下文切换来剪切图形基元的装置，系统和方法
公开(公告)号：US08432406B1
公开(公告)日：2013-04-30
申请号：US12182588
申请日：2008-07-30
申请人： Lordson L. Yue , Vimal S. Parikh
发明人： Lordson L. Yue , Vimal S. Parikh
IPC分类号： G06T1/20
CPC分类号： G09G5/363 , G06T1/20
摘要： An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit that is configured to produce and issue ni initial outputs based on execution of a set of clipping operations, wherein ni represents the number of the initial outputs that are issued by the clipping unit prior to context switching, and the initial outputs partially define a clipped graphics primitive. The graphics processing apparatus also includes a control unit connected to the clipping unit. The control unit is configured to preserve an initial execution state of the clipping unit in response to an initial command for context switching, wherein the initial execution state is preserved based on ni.
摘要翻译：描述用于剪切图形基元的装置，系统和方法。在一个实施例中，图形处理装置包括剪辑单元，其被配置为基于执行一组剪切操作来产生和发出ni初始输出，其中ni表示由剪辑单元在之前发出的初始输出的数量上下文切换，并且初始输出部分地限定剪切的图形原语。图形处理装置还包括连接到裁剪单元的控制单元。控制单元被配置为响应于用于上下文切换的初始命令来保留剪切单元的初始执行状态，其中基于ni来保留初始执行状态。

4. 发明授权

US07420572B1 Apparatus, system, and method for clipping graphics primitives with accelerated context switching 有权
标题翻译：用于通过加速上下文切换来剪切图形基元的装置，系统和方法
公开(公告)号：US07420572B1
公开(公告)日：2008-09-02
申请号：US11313085
申请日：2005-12-19
申请人： Lordson L. Yue , Vimal S. Parikh
发明人： Lordson L. Yue , Vimal S. Parikh
IPC分类号： G09G5/00 , G06T1/20
CPC分类号： G09G5/363 , G06T1/20
摘要： An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit that is configured to issue an initial set of outputs based on execution of a set of clipping operations. The graphics processing apparatus also includes a control unit that is connected to the clipping unit. The control unit is configured to preserve an initial execution state of the clipping unit in response to an initial command for context switching, and the initial execution state is preserved based on a number of the initial set of outputs.
摘要翻译：描述用于剪切图形基元的装置，系统和方法。在一个实施例中，图形处理装置包括限幅单元，其被配置为基于一组剪切操作的执行来发出初始输出集合。图形处理装置还包括连接到剪辑单元的控制单元。控制单元被配置为响应于用于上下文切换的初始命令来保留剪切单元的初始执行状态，并且基于初始输出集合的数量来保留初始执行状态。

5. 发明授权

US07292254B1 Apparatus, system, and method for clipping graphics primitives with reduced sensitivity to vertex ordering 有权
标题翻译：用于削减对顶点排序灵敏度降低的图形图元的装置，系统和方法
公开(公告)号：US07292254B1
公开(公告)日：2007-11-06
申请号：US11294791
申请日：2005-12-05
申请人： Lordson L. Yue , Vimal S. Parikh , Andrew J. Tao
发明人： Lordson L. Yue , Vimal S. Parikh , Andrew J. Tao
IPC分类号： G09G5/00 , G06T1/00
CPC分类号： G06T15/30
摘要： Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a mapping unit and a clipping engine that is connected to the mapping unit. The mapping unit is configured to map a graphics primitive onto a canonical representation. The clipping engine is configured to perform a set of clipping operations with respect to the canonical representation.
摘要翻译：描述用于剪切图形基元的装置，系统和方法。在一个实施例中，图形处理装置包括连接到映射单元的映射单元和剪辑引擎。映射单元被配置为将图形原语映射到规范表示。剪辑引擎被配置为执行关于规范表示的一组剪切操作。

6. 发明授权

US07714877B1 Apparatus, system, and method for determining clipping distances 有权
标题翻译：用于确定剪切距离的装置，系统和方法
公开(公告)号：US07714877B1
公开(公告)日：2010-05-11
申请号：US11312965
申请日：2005-12-19
申请人： Vimal S. Parikh , Lordson L. Yue
发明人： Vimal S. Parikh , Lordson L. Yue
IPC分类号： G09G5/00
CPC分类号： G09G5/363 , G06T15/30 , G09G2360/06
摘要： An apparatus, system, and method for determining clipping distances are described. In one embodiment, a graphics processing apparatus includes a clipping unit and an instruction memory connected to the clipping unit. The instruction memory includes a clipping program to direct the clipping unit to perform clipping operations. The clipping program includes a clipping distance instruction to determine a clipping distance with respect to any of a set of clipping planes.
摘要翻译：描述用于确定剪切距离的装置，系统和方法。在一个实施例中，图形处理装置包括剪切单元和连接到剪辑单元的指令存储器。指令存储器包括用于指示剪切单元进行剪切操作的剪切程序。剪切程序包括剪切距离指令，用于确定相对于一组剪切平面中的任何一个的剪切距离。

7. 发明授权

US07616218B1 Apparatus, system, and method for clipping graphics primitives 有权
标题翻译：用于剪切图形图元的装置，系统和方法
公开(公告)号：US07616218B1
公开(公告)日：2009-11-10
申请号：US11295355
申请日：2005-12-05
申请人： Vimal S. Parikh , Andrew J. Tao , Lordson L. Yue
发明人： Vimal S. Parikh , Andrew J. Tao , Lordson L. Yue
IPC分类号： G09G5/00
CPC分类号： G06F12/1027
摘要： Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a clipping module includes a clipping engine and a clipping controller connected to the clipping engine. The clipping controller is configured to determine which edges of an input graphics primitive intersect a first clipping plane. The clipping controller is configured to direct the clipping engine to clip, with respect to the first clipping plane, a first pair of edges of the input graphics primitive in response to determining that the first pair of edges intersect the first clipping plane.
摘要翻译：描述用于剪切图形基元的装置，系统和方法。在一个实施例中，剪辑模块包括剪辑引擎和连接到剪辑引擎的剪辑控制器。剪辑控制器被配置为确定输入图形基元的哪些边缘与第一剪切平面相交。剪辑控制器被配置为响应于确定第一对边缘与第一剪切平面相交而引导剪辑引擎相对于第一剪辑平面剪辑输入图形图元的第一对边缘。

8. 发明授权

US5036528A Self-calibrating clock synchronization system 失效
标题翻译：自校准时钟同步系统
公开(公告)号：US5036528A
公开(公告)日：1991-07-30
申请号：US471915
申请日：1990-01-29
申请人： Duc N. Le , Lordson L. Yue , Cirillo L. Costantino , David P. Chengson , Duc N. Le , Lordson L. Yue , Aurangzeb K. Khan
发明人： Duc N. Le , Lordson L. Yue , Cirillo L. Costantino , David P. Chengson , Duc N. Le , Lordson L. Yue , Aurangzeb K. Khan
IPC分类号： G06F1/12 , G06F1/10 , H03K5/00
CPC分类号： G06F1/10
摘要： The present invention is directed to a self-calibrating clock synchronization system that receives a periodic, digital clock signal as a reference and generates therefrom a system clock signal that dynamically tracks and is synchronized to the reference clock. The invention utilizes state machine controlled selection circuitry that comprises a plurality of predetermined delays tapped to produce a number of phase-related clock signals, and multiplexing circuitry, for selecting one of the plurality of clock signals as the system clock. A comparator compares the selected clock signal and the reference clock to determine which leads or lags the other. In response to the comparison, selection, from the plurality of clock signals, of a system clock that most clearly matches the reference signal is made.

9. 发明授权

US07224364B1 Optimal initial rasterization starting point 有权
标题翻译：最佳初始光栅化起始点
公开(公告)号：US07224364B1
公开(公告)日：2007-05-29
申请号：US09244270
申请日：1999-02-03
申请人： Lordson L. Yue , James T. Battle
发明人： Lordson L. Yue , James T. Battle
IPC分类号： G06T11/00 , G06T11/20
CPC分类号： G06T15/005
摘要： A frame buffer is divided into tiles of, for example, 32 by 32 pixels. Triangles (and portions thereof) that are within a given tile are rasterized one triangle at a time into the tile location. This process repeats for each tile in the image frame. A sorting circuit generates control bits representing a vertical order of the vertices of a current triangle. A series of multiplexers vertically sorts the vertices bases on these control bits. A region calculation circuit generates region bits representing a location each of the vertices with respect to the current tile. A trivial discard of the triangle data occurs if the region bits indicate that the entire triangle lies outside of the tile. Subsequently, an initial rasterization starting point is estimated based on the region bits to lower the time needed for the rasterizer to find the first pixel of the current triangle to be assigned values.
摘要翻译：帧缓冲器被划分为例如32×32像素的瓦片。在给定瓦片内的三角形（及其部分）一次被一个三角形光栅化到瓦片位置。该过程对于图像帧中的每个图块重复。排序电路产生表示当前三角形的顶点的垂直顺序的控制位。一系列多路复用器将这些控制位上的顶点垂直排列。区域计算电路产生表示相对于当前瓦片的每个顶点的位置的区域位。如果区域位指示整个三角形位于瓦片之外，则会发生三角形数据的平凡丢弃。随后，基于区域比特来估计初始光栅化起始点，以降低光栅化器找到要分配值的当前三角形的第一像素所需的时间。

10. 发明授权

US4951050A 2:1 Voltage matrix encoded I/O transmission system 失效
标题翻译： 2：1电压矩阵编码的I / O传输系统
公开(公告)号：US4951050A
公开(公告)日：1990-08-21
申请号：US268422
申请日：1988-11-08
申请人： Aurangzeb K. Khan , Lordson L. Yue
发明人： Aurangzeb K. Khan , Lordson L. Yue
IPC分类号： H03M5/20
CPC分类号： H03M5/20
摘要： Encoding and decoding circuits, utilizing high speed ECL-like logic, simultaneously transmit and receive multiple binary signals via a single I/O pin.
摘要翻译：使用高速ECL逻辑的编码和解码电路通过单个I / O引脚同时发送和接收多个二进制信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式