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1. 发明申请

US20080082711A1 System and method for managing system management interrupts in a multiprocessor computer system 有权
标题翻译：用于管理多处理器计算机系统中的系统管理中断的系统和方法
公开(公告)号：US20080082711A1
公开(公告)日：2008-04-03
申请号：US11540805
申请日：2006-09-29
申请人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
发明人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F11/0724 , G06F11/0757 , G06F2209/481
摘要： A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.
摘要翻译：公开了一种用于管理多处理器系统中的系统管理中断的系统和方法。本文描述的系统包括多个处理器，每个处理器可以直接耦合到存储器。主处理器将识别系统管理中断的启动。主处理器将将原因码写入存储位置并设置看门狗定时器，其到期将使系统的所有处理器进入系统管理模式。在所有处理器进入系统管理模式之后，确定存储位置的原因代码是否与某些基于软件的系统管理中断相对应。如果是这样，系统管理中断由本地处理器处理。在本地处理器处理系统管理中断之后，向每个其他处理器发送一个信号，使处理器退出系统管理模式。

2. 发明申请

US20080082710A1 System and method for managing system management interrupts in a multiprocessor computer system 审中-公开
标题翻译：用于管理多处理器计算机系统中的系统管理中断的系统和方法
公开(公告)号：US20080082710A1
公开(公告)日：2008-04-03
申请号：US11540804
申请日：2006-09-29
申请人： Vijay Nijhawan , Madhusudhan Rangarajan , Bi-Chong Wang , Wuxian Wu
发明人： Vijay Nijhawan , Madhusudhan Rangarajan , Bi-Chong Wang , Wuxian Wu
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/4812
摘要： A system and method is disclosed in which, during the execution of an interrupt handling sequence in one of the processor of a multiprocessor system, a processors write a reason code to a status register to identify the cause of the interrupt. The BIOS code of the system writes to an interrupt initiation register to cause each of the processors to enter an interrupt handling sequence. Each of the processors of the system handling the interrupt on the basis of the content of the status register, resulting in each of the processors synchronously handling an interrupt for an event that would otherwise result in a local interrupt.
摘要翻译：公开了一种系统和方法，其中在多处理器系统的处理器之一执行中断处理序列期间，处理器将原因代码写入状态寄存器以识别中断的原因。系统的BIOS代码写入中断启动寄存器，使每个处理器进入中断处理程序。基于状态寄存器的内容处理中断的系统的每个处理器，导致每个处理器同步处理否则将导致本地中断的事件的中断。

3. 发明授权

US07721034B2 System and method for managing system management interrupts in a multiprocessor computer system 有权
标题翻译：用于管理多处理器计算机系统中的系统管理中断的系统和方法
公开(公告)号：US07721034B2
公开(公告)日：2010-05-18
申请号：US11540805
申请日：2006-09-29
申请人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
发明人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F11/0724 , G06F11/0757 , G06F2209/481
摘要： A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.
摘要翻译：公开了一种用于管理多处理器系统中的系统管理中断的系统和方法。本文描述的系统包括多个处理器，每个处理器可以直接耦合到存储器。主处理器将识别系统管理中断的启动。主处理器将将原因码写入存储位置并设置看门狗定时器，其到期将使系统的所有处理器进入系统管理模式。在所有处理器进入系统管理模式之后，确定存储位置的原因代码是否与某些基于软件的系统管理中断相对应。如果是这样，系统管理中断由本地处理器处理。在本地处理器处理系统管理中断之后，向每个其他处理器发送一个信号，使处理器退出系统管理模式。

4. 发明申请

US20080028117A1 Method and Apparatus for Notifying User About Non-Optimal Hot-Add Memory Configurations 审中-公开
标题翻译：用于通知用户关于非最佳热添加存储器配置的方法和装置
公开(公告)号：US20080028117A1
公开(公告)日：2008-01-31
申请号：US11460056
申请日：2006-07-26
申请人： Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
发明人： Vijay Nijhawan , Madhusudhan Rangarajan , Wuxian Wu
IPC分类号： G06F13/00
CPC分类号： G06F12/06 , G06F13/4081 , G06F2212/1016
摘要： During power-on self-test (POST) the basic input-output operating system (BIOS) may set hot-add status light emitting diodes (LEDs) to appropriate colors so as to indicate which memory slot(s) is most optimal for hot-adding a hot-plug memory module. In the case where the user or administrator fails to notice or understand the meaning of the LED color representation when hot-adding the new memory module, the BIOS Service Management Initiative (SMI) handler (which controls the hot-add to the information handling system) will verify if the hot-add memory module is being installed into an optimal memory slot. If not, the BIOS may capture a Chassis System Event Log (SEL) indicating a non-optimal Hot-add and may flash a front panel LED to a certain color, e.g., amber, and may also issue an appropriate error message. Additional Advanced Configuration and Power Interface (ACPI) implementations may be used for a more user-friendly alert and/or message display.
摘要翻译：在开机自检（POST）期间，基本输入输出操作系统（BIOS）可以将热添加状态发光二极管（LED）设置为适当的颜色，以指示哪些内存插槽最适合热 - 添加热插拔内存模块。在热添加新内存模块时，用户或管理员无法注意或了解LED颜色表示的含义的情况下，BIOS服务管理计划（SMI）处理程序（其控制热添加到信息处理系统）将验证热添加内存模块是否正在安装到最佳内存插槽中。如果没有，则BIOS可能会捕获指示非最佳热添加的底盘系统事件日志（SEL），并可能会将前面板LED闪烁到某种颜色（例如琥珀色），并且还可能会发出适当的错误消息。附加的高级配置和电源接口（ACPI）实现可以用于更加用户友好的警报和/或消息显示。

5. 发明申请

US20070083728A1 System and method for enumerating multi-level processor-memory affinities for non-uniform memory access systems 有权
标题翻译：用于枚举非均匀内存访问系统的多级处理器内存亲和度的系统和方法
公开(公告)号：US20070083728A1
公开(公告)日：2007-04-12
申请号：US11247036
申请日：2005-10-11
申请人： Vijay Nijhawan , Saurabh Gupta , Bi-Chong Wang , Wuxian Wu
发明人： Vijay Nijhawan , Saurabh Gupta , Bi-Chong Wang , Wuxian Wu
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F9/5016 , G06F2212/2542
摘要： A system and method is disclosed for enumerating multi-level processor-memory affinities for non-uniform memory access systems. A processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in an information-handling system is calculated using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system. The information-handling system then performs an algorithm on each processor-memory affinity hierarchy to obtain processor-memory affinity values in the information-handling system, and populates a table using the processor-memory affinity values. An operating system in the information-handling system can use the table to allocate memory units among microprocessors in the information-handling system.
摘要翻译：公开了一种用于枚举用于非均匀存储器访问系统的多级处理器 - 存储器亲和度的系统和方法。使用描述如何将微处理器和存储器单元布置在信息处理系统中的存储器访问速度的至少两个特性来计算处理器 - 存储器亲和层次结构，用于信息处理系统中的微处理器和存储器单元的每个可能的配对。处理系统。然后，信息处理系统在每个处理器 - 存储器亲和层级上执行算法，以在信息处理系统中获得处理器 - 存储器相关性值，并且使用处理器 - 存储器亲和度值来填充表格。信息处理系统中的操作系统可以使用该表来在信息处理系统中的微处理器之间分配存储单元。

6. 发明授权

US07734905B2 System and method for preventing an operating-system scheduler crash 有权
标题翻译：防止操作系统调度程序崩溃的系统和方法
公开(公告)号：US07734905B2
公开(公告)日：2010-06-08
申请号：US11405229
申请日：2006-04-17
申请人： Bi-Chong Wang , Wuxian Wu
发明人： Bi-Chong Wang , Wuxian Wu
IPC分类号： G06F13/24 , G06F15/177
CPC分类号： G06F9/4825
摘要： System and methods for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt are disclosed. A periodic interrupt is generated using a real-time clock (RTC) residing on a chipset. A flag indicating a periodic interrupt is entered into a status register associated with the RTC in firmware residing on the CMOS chip, if the status register indicates no periodic interrupt has been pending. An interrupt handler associated with the RTC attempts to handle the periodic interrupt, if pending. If the periodic interrupt is pending after a preset interval of time elapses, a basic-input-output system (BIOS) residing on a memory unit coupled to the chipset generates a system-management interrupt (SMI). If the periodic interrupt is pending after the preset interval of time elapses, a firmware SMI handler residing on the memory unit clears the pending periodic interrupts from the status register. A scheduler timer associated with the operating system is updated.
摘要翻译：公开了用于防止计算机系统中的操作系统调度器由于未清除的周期性中断而导致的崩溃的系统和方法。使用驻留在芯片组上的实时时钟（RTC）产生周期性中断。如果状态寄存器指示没有周期性中断已经挂起，则表示周期性中断的标志被输入到驻留在CMOS芯片上的固件中与RTC相关联的状态寄存器。与RTC相关联的中断处理程序尝试处理周期性中断，如果挂起。如果在预设的时间间隔过后周期性中断待处理，驻留在与芯片组耦合的存储器单元上的基本输入输出系统（BIOS）产生系统管理中断（SMI）。如果在预设时间间隔过后周期性中断待处理，驻留在存储器单元上的固件SMI处理器将从状态寄存器清除待处理的周期性中断。与操作系统相关联的调度器定时器被更新。

7. 发明申请

US20070245054A1 System and method for preventing an operating-system scheduler crash 有权
标题翻译：防止操作系统调度程序崩溃的系统和方法
公开(公告)号：US20070245054A1
公开(公告)日：2007-10-18
申请号：US11405229
申请日：2006-04-17
申请人： Bi-Chong Wang , Wuxian Wu
发明人： Bi-Chong Wang , Wuxian Wu
IPC分类号： G06F13/24 , G06F15/177
CPC分类号： G06F9/4825
摘要： System and methods for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt are disclosed. A periodic interrupt is generated using a real-time clock (RTC) residing on a chipset. A flag indicating a periodic interrupt is entered into a status register associated with the RTC in firmware residing on the CMOS chip, if the status register indicates no periodic interrupt has been pending. An interrupt handler associated with the RTC attempts to handle the periodic interrupt, if pending. If the periodic interrupt is pending after a preset interval of time elapses, a basic-input-output system (BIOS) residing on a memory unit coupled to the chipset generates a system-management interrupt (SMI). If the periodic interrupt is pending after the preset interval of time elapses, a firmware SMI handler residing on the memory unit clears the pending periodic interrupts from the status register. A scheduler timer associated with the operating system is updated.
摘要翻译：公开了用于防止计算机系统中的操作系统调度器由于未清除的周期性中断而导致的崩溃的系统和方法。使用驻留在芯片组上的实时时钟（RTC）产生周期性中断。如果状态寄存器指示没有周期性中断已经挂起，则表示周期性中断的标志被输入到驻留在CMOS芯片上的固件中与RTC相关联的状态寄存器。与RTC相关联的中断处理程序尝试处理周期性中断，如果挂起。如果在预设的时间间隔过后周期性中断待处理，驻留在与芯片组耦合的存储器单元上的基本输入输出系统（BIOS）产生系统管理中断（SMI）。如果在预设时间间隔过后周期性中断待处理，驻留在存储器单元上的固件SMI处理器将从状态寄存器清除待处理的周期性中断。与操作系统相关联的调度器定时器被更新。

8. 发明授权

US06904546B2 System and method for interface isolation and operating system notification during bus errors 有权
标题翻译：总线错误时接口隔离和操作系统通知的系统和方法
公开(公告)号：US06904546B2
公开(公告)日：2005-06-07
申请号：US10074204
申请日：2002-02-12
申请人： Wuxian Wu , Paul Dennis Stultz , Madhusudhan Rangarajan
发明人： Wuxian Wu , Paul Dennis Stultz , Madhusudhan Rangarajan
IPC分类号： G06F11/00 , G06F11/07 , G06F13/14
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0793
摘要： A system and method for notifying an operating system of an error signal transmitted by a communications medium is disclosed. The communications medium connects a plurality of electronic devices. The operating system includes device drivers and is capable of configuring communications between one or more applications and the communications medium. A detector is coupled to the communications medium. The detector receives error signals transmitted by the communications medium, one or more error signals associated with one of the electronic devices. A BIOS is coupled to the detector. The BIOS is capable of determining an electronic device associated with a first error signal. The BIOS generates a hot-eject signal identifying that electronic device in response to the first error signal. The operating system blocks communications between the applications and the identified electronic device in response to the BIOS generating the hot-eject signal.
摘要翻译：公开了一种用于通知操作系统由通信介质发送的错误信号的系统和方法。通信介质连接多个电子设备。操作系统包括设备驱动器，并且能够配置一个或多个应用与通信介质之间的通信。检测器耦合到通信介质。检测器接收由通信介质发送的错误信号，与一个电子设备相关联的一个或多个错误信号。 BIOS耦合到检测器。 BIOS能够确定与第一错误信号相关联的电子设备。 BIOS响应于第一错误信号产生识别该电子设备的热排出信号。操作系统响应于生成热喷射信号的BIOS阻止应用和识别的电子设备之间的通信。

9. 发明授权

US07577813B2 System and method for enumerating multi-level processor-memory affinities for non-uniform memory access systems 有权
标题翻译：用于枚举非均匀内存访问系统的多级处理器内存亲和度的系统和方法
公开(公告)号：US07577813B2
公开(公告)日：2009-08-18
申请号：US11247036
申请日：2005-10-11
申请人： Vijay B. Nijhawan , Saurabh Gupta , Bi-Chong Wang , Wuxian Wu
发明人： Vijay B. Nijhawan , Saurabh Gupta , Bi-Chong Wang , Wuxian Wu
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F9/5016 , G06F2212/2542
摘要： A system and method is disclosed for enumerating multi-level processor-memory affinities for non-uniform memory access systems. A processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in an information-handling system is calculated using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system. The information-handling system then performs an algorithm on each processor-memory affinity hierarchy to obtain processor-memory affinity values in the information-handling system, and populates a table using the processor-memory affinity values. An operating system in the information-handling system can use the table to allocate memory units among microprocessors in the information-handling system.
摘要翻译：公开了一种用于枚举用于非均匀存储器访问系统的多级处理器 - 存储器亲和度的系统和方法。使用描述如何将微处理器和存储器单元布置在信息处理系统中的存储器访问速度的至少两个特性来计算处理器 - 存储器亲和层次结构，用于信息处理系统中的微处理器和存储器单元的每个可能的配对。处理系统。然后，信息处理系统在每个处理器 - 存储器亲和层级上执行算法，以在信息处理系统中获得处理器 - 存储器相关性值，并且使用处理器 - 存储器亲和度值来填充表格。信息处理系统中的操作系统可以使用该表来在信息处理系统中的微处理器之间分配存储单元。

10. 发明申请

US20120179938A1 Methods and Systems for Managing Performance and Power Utilization of a Processor Employing a Fully Multithreaded Load Threshold 有权
标题翻译：用于管理使用完全多线程负载阈值的处理器性能和功耗的方法和系统
公开(公告)号：US20120179938A1
公开(公告)日：2012-07-12
申请号：US12987591
申请日：2011-01-10
申请人： Vijay Nijhawan , Gregory N. Darnell , Wuxian Wu
发明人： Vijay Nijhawan , Gregory N. Darnell , Wuxian Wu
IPC分类号： G06F11/07 , G06F15/177
CPC分类号： G06F1/3234 , G06F1/3206 , G06F1/324 , G06F1/329 , G06F9/4806 , G06F11/00 , G06F11/3017 , G06F11/3409 , G06F2201/81 , G06F2201/86 , Y02D10/126 , Y02D10/34
摘要： A method for managing performance and power utilization of a processor in an information handling system (IHS) employing a balanced fully-multithreaded load threshold is disclosed. The method includes providing a maximum current thread utilization (Umax) and a minimum current thread utilization (Umin) among all current thread utilizations of the processor and determining a current performance state (P state) of the processor. The method also includes increasing a current P state of the processor to a next P state of the processor towards a maximum P state (Pmax) of the processor when the current P state of the processor is between Umax and Umin and the current utilization rate of the processor is less than a first threshold utilization rate. The method further includes engaging the processor in a turbo mode when the current P state of the processor reaches the Pmax and the current utilization of the processor is greater than the first threshold utilization rate of the processor.
摘要翻译：公开了一种在采用平衡完全多线程负载阈值的信息处理系统（IHS）中管理处理器的性能和功率利用的方法。该方法包括在处理器的所有当前线程利用率中提供最大当前线程利用率（Umax）和最小当前线程利用率（Umin），并确定处理器的当前性能状态（P状态）。该方法还包括当处理器的当前P状态在Umax和Umin之间时将处理器的当前P状态增加到处理器的下一个P状态朝向处理器的最大P状态（Pmax），并且当前利用率处理器小于第一阈值利用率。该方法还包括当处理器的当前P状态达到Pmax并且处理器的当前利用率大于处理器的第一阈值利用率时，以turbo模式接合处理器。

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