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1. 发明授权

US07480877B2 Methods and apparatus for Boolean equivalency checking in the presence of voting logic 失效
标题翻译：在存在投票逻辑的情况下进行布尔等价检查的方法和装置
公开(公告)号：US07480877B2
公开(公告)日：2009-01-20
申请号：US11463958
申请日：2006-08-11
申请人： Victor A. Acuña , Robert L. Kanzelman , Scott H. Mack , Brian C. Wilson
发明人： Victor A. Acuña , Robert L. Kanzelman , Scott H. Mack , Brian C. Wilson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/31835
摘要： In a first aspect, a first method of designing a circuit is provided. The first method includes the steps of (1) providing a model of an original circuit design including a latch; (2) providing a model of a modified version of the original circuit design, wherein the modified version of the original circuit design includes a set of latches associated with the latch of the original circuit design and voting logic having inputs coupled to respective outputs of latches in the latch set; and (3) during Boolean equivalency checking (BEC), injecting an error on at most a largest minority of the inputs of the voting logic to test the voting logic function.
摘要翻译：在第一方面，提供了设计电路的第一种方法。第一种方法包括以下步骤：（1）提供包括闩锁的原始电路设计的模型; （2）提供原始电路设计的修改版本的模型，其中原始电路设计的修改版本包括与原始电路设计的锁存器相关联的一组锁存器和具有耦合到锁存器的相应输出的输入的投票逻辑在锁定组中; 和（3）在布尔等价性检查（BEC）期间，在表决逻辑的最多输入的最多少量输入错误，以测试投票逻辑功能。

2. 发明申请

US20130159591A1 VERIFYING DATA RECEIVED OUT-OF-ORDER FROM A BUS 审中-公开
标题翻译：验证从总线接收到的数据
公开(公告)号：US20130159591A1
公开(公告)日：2013-06-20
申请号：US13325701
申请日：2011-12-14
申请人： Victor A. Acuña , Mark J. Hickey , Galen A. Lyle , Ibrahim A. Ouda
发明人： Victor A. Acuña , Mark J. Hickey , Galen A. Lyle , Ibrahim A. Ouda
IPC分类号： G06F13/36
CPC分类号： G06F11/221
摘要： In an embodiment, load transactions are issued to a bus. The load transactions are stalled if the bus cannot accept additional load transactions, and the load transactions are restarted after the bus can accept the additional load transactions. Responses are received from the bus to the load transactions out-of-order from an order that the load transactions were sent to the bus. The responses comprise data and index values that indicate an order that the load transactions were received by the bus. The data is compared in the order that the load transactions were received by the bus against expected data in the order that the load transaction were sent to the bus.
摘要翻译：在一个实施例中，向总线发出负载事务。如果总线不能接受额外的负载事务，负载事务将停止，并且在总线接受额外的负载事务之后重新启动负载事务。从总线接收到从负载事务发送到总线的命令无序的负载事务的响应。响应包括指示负载事务被总线接收的顺序的数据和索引值。将数据按照负载事务按照载入事务发送到总线的顺序由总线接收到预期数据的顺序进行比较。

3. 发明申请

US20130185477A1 VARIABLE LATENCY MEMORY DELAY IMPLEMENTATION 审中-公开
标题翻译：可变延迟内存延迟执行
公开(公告)号：US20130185477A1
公开(公告)日：2013-07-18
申请号：US13352619
申请日：2012-01-18
申请人： Victor A. Acuña , Dale L. Elson , Mark J. Hickey , Galen A. Lyle , Ibrahim A. Ouda
发明人： Victor A. Acuña , Dale L. Elson , Mark J. Hickey , Galen A. Lyle , Ibrahim A. Ouda
IPC分类号： G06F12/00
CPC分类号： G06F11/263
摘要： A method includes receiving, from a processor, a first read request mapped including a first read request address to a first memory location of a register array and a second read request including a second read request address to a second memory location of a register array. The method includes assigning a first simulated time delay to the first read request and assigning a second simulated time delay to the second read request. The method includes, in response to a first elapsed time being equal to the first simulated time delay, outputting a first read request response including first data. The first elapsed time commences upon receipt of the first read request. The method includes, in response to a second elapsed time being equal to the second simulated time delay, outputting a second read request response including second data. The second elapsed time commences upon receipt of the second read request.
摘要翻译：一种方法包括从处理器接收包括第一读取请求地址的第一读取请求到寄存器阵列的第一存储器位置以及包括第二读取请求地址的第二读取请求到寄存器阵列的第二存储器位置。该方法包括将第一模拟时间延迟分配给第一读取请求并将第二模拟时间延迟分配给第二读取请求。该方法包括响应于第一经过时间等于第一模拟时间延迟，输出包括第一数据的第一读请求响应。第一次经过的时间在收到第一个读取请求后开始。该方法包括响应于第二经过时间等于第二仿真时间延迟，输出包括第二数据的第二读请求响应。第二个经过时间在收到第二个读取请求后开始。

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