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1. 发明申请

US20150352767A1 Fabrication of Porous Carbon Nanofibers with Large Power Handling Capability 审中-公开
标题翻译：具有大功率处理能力的多孔碳纳米纤维的制备
公开(公告)号：US20150352767A1
公开(公告)日：2015-12-10
申请号：US13688296
申请日：2012-11-29
申请人： Vibha Kalra , Chau Tran
发明人： Vibha Kalra , Chau Tran
IPC分类号： B29C47/00 , D01F9/14 , D01F9/22
CPC分类号： D01F9/22 , B29K2077/10 , B29L2031/731 , D01D5/003 , D01D5/247 , D01D10/02 , D01F1/08 , D01F11/10 , Y10T428/2918
摘要： A method for producing porous nanofibers having tunable meso- and micropores, and the articles produced by the method. In some embodiments, the method comprises electrospinning a polymer blend comprising polyacrylonitrile and a sulfonated polymer dissolved in a solvent to form a fibers; heat treating the mat or web of fibers sequentially at first, second, and optionally third temperatures; and optionally treating the heat treated fibers with an oxidizing agent.
摘要翻译：一种具有可调谐的中孔和微孔的多孔纳米纤维的制造方法以及通过该方法制造的制品。在一些实施方案中，该方法包括将包含聚丙烯腈和溶解在溶剂中的磺化聚合物的聚合物共混物静电纺丝以形成纤维; 在第一，第二和任选的第三温度下顺序地热处理纤维网或纤维网; 并任选地用氧化剂处理热处理的纤维。

2. 发明申请

US20070205295A1 Temperature setpoint circuit with hysteresis 有权
标题翻译：带迟滞的温度设定电路
公开(公告)号：US20070205295A1
公开(公告)日：2007-09-06
申请号：US11370155
申请日：2006-03-06
申请人： Chau Tran , A. Brokaw
发明人： Chau Tran , A. Brokaw
IPC分类号： F23N5/20 , G05D23/00
CPC分类号： G05D23/1904 , Y10S323/907
摘要： A temperature setpoint circuit comprises bipolar transistors Q1 and Q2 which receive currents I1 and I2 at their respective collectors and are operated at unequal current densities, with a resistance R1 connected between their bases such that the difference in their base-emitter voltages (ΔVbe) appears across R1. An additional PTAT current I3 is maintained in a constant ratio to I1 and I2 and provided to the collector of Q2 while Q2 is off, and is not provided while Q2 is on. The circuit is arranged such that Q2 is turned on and conducts a current equal to Ia when: ΔVbe=(kT/q)ln(NI1/Ia), where Ia=I2+I3, the temperature T at which ΔVbe=(kT/q)ln(NI1/Ia) being the circuit's setpoint temperature, such that the switching of current I3 provides hysteresis for the setpoint temperature which is approximately constant over temperature.
摘要翻译：温度设定点电路包括在其各自的集电极处接收电流I 1和I 2并且以不相等的电流密度工作的双极晶体管Q 1和Q 2，其电阻R 1连接在它们的基极之间，使得它们的基极 - 发射极电压（DeltaV ）出现在R 1上。另外的PTAT电流I 3以与I 1和I 2恒定的比例保持，并且在Q 2断开时提供给Q 2的集电极，并且在Q 2接通时不提供。电路被布置为使得Q 2导通，并且当以下情况下导通等于Ia的电流：ΔV=（kT / q）ln（NI 1 / Ia），其中Ia = I 2 + I 如图3所示，DeltaV =（kT / q）ln（NI 1 / Ia）的温度T是电路的设定点温度，使得电流I 3的切换为设定点温度提供迟滞在温度范围内大致恒定。

3. 发明申请

US20050139892A1 Repatterned integrated circuit chip package 有权
公开(公告)号：US20050139892A1
公开(公告)日：2005-06-30
申请号：US11067795
申请日：2005-02-28
申请人： Moshe Gerstenhaber , Chau Tran
发明人： Moshe Gerstenhaber , Chau Tran
IPC分类号： H01L23/50 , H03F3/45 , H01L27/108
CPC分类号： H03F3/45475 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H03F3/45991 , H03F2200/261 , H01L2924/00
摘要： A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency.

4. 发明授权

US08572302B1 Controller for storage device with improved burst efficiency 有权
标题翻译：具有提高突发效率的存储设备控制器
公开(公告)号：US08572302B1
公开(公告)日：2013-10-29
申请号：US11872673
申请日：2007-10-15
申请人： Theodore White , Stanley Cheong , Lim Hudiono , William Dennin, III , Chau Tran
发明人： Theodore White , Stanley Cheong , Lim Hudiono , William Dennin, III , Chau Tran
IPC分类号： G06F13/00
CPC分类号： G06F13/28 , G06F5/10 , G06F11/1016 , G06F13/385 , G06F2213/3802
摘要： A controller and a method for interfacing between a host and storage medium. A storage medium interface includes CH0 circuitry for performing a CH0 process to access a buffer memory on behalf of the storage medium. A host interface includes CH1 circuitry for performing a CH1 process to access the buffer memory on behalf of the host. Access to the buffer memory is arbitrated in sequential tenures to each channel of the multi-channel bus within a maximum arbitration round trip time defined by the time taken by the storage medium to move a distance corresponding to N sectors in which N is greater than one. In the CH0 tenure, the CH0 process transfers data corresponding to N sectors of the storage medium in a multi-sector burst. The length of the tenure of the CH0 channel is pre-designated so that the multi-sector burst is completed within the CH0 tenure.
摘要翻译：用于在主机和存储介质之间进行接口的控制器和方法。存储介质接口包括用于执行CH0处理以代表存储介质访问缓冲存储器的CH0电路。主机接口包括CH1电路，用于执行CH1处理以代表主机访问缓冲存储器。在由存储介质移动对应于其中N大于1的N个扇区的距离所限定的最大仲裁往返时间的最大仲裁往返时间内，对缓冲存储器的访问顺序进行仲裁到多信道总线的每个信道。在CH0任期中，CH0处理以多扇区突发传送对应于存储介质的N个扇区的数据。预先指定CH0通道的任期，以便在CH0任期内完成多扇区突发。

5. 发明申请

US20070001758A1 Multiple differential amplifier system and method for transconductance mismatch compensation 有权
公开(公告)号：US20070001758A1
公开(公告)日：2007-01-04
申请号：US11172186
申请日：2005-06-30
申请人： Alasdair Alexander , Chau Tran
发明人： Alasdair Alexander , Chau Tran
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F1/14 , H03F3/45968 , H03F2200/261 , H03F2203/45288 , H03F2203/45551
摘要： A multiple differential amplifier system and method for transconductance mismatch compensation which in a first phase connects to a differential switched input of a null amplifier, the differential signal input of the main amplifier, inverted, for compensating for offset errors and transconductance mismatches in the null amplifier; and storing in a null storage device connected to an auxiliary input of the null amplifier the output of the null amplifier representing the compensation for the offset error and transconductance mismatch of the null amplifier; and in a second phase connecting the differential switched input of the null amplifier to the differential feedback input of the main amplifier and storing in the main storage device connected to an auxiliary input of the main amplifier the output of the null amplifier representing the compensation for the main amplifier offset error and transconductance mismatch.

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