专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09712848B2 Frame buffer compression using separate aggregation of fixed-length and variable-length components of codewords 有权
公开(公告)号：US09712848B2
公开(公告)日：2017-07-18
申请号：US14536859
申请日：2014-11-10
申请人： ViXS Systems Inc.
发明人： Wendy Wai Yin Cheung , Xin Guo
IPC分类号： H04N19/91 , H04N19/88 , H03M7/40
CPC分类号： H04N19/91 , H03M7/4031 , H04N19/88
摘要： Each set of pels of an image frame is encoded into a corresponding set of codewords having fixed-length and unary variable-length components. The variable-length components are combined into a variable-length portion and the fixed-length components are separately combined into a fixed-length portion that is attached to the variable-length portion to complete a bit segment. For decompression, a first bit string of a fixed number of bits is identified as a fixed-length portion of the bit segment. A search window placed adjacent to the first bit string is scanned to find a second bit string having a number of termination bits equal to the number of codewords in the set, with the second bit string thus representing the variable-length portion of a corresponding bit segment. Each variable-length component of the identified variable-length portion is combined with a corresponding fixed-length component of the identified fixed-length portion to recreate a corresponding codeword.

2. 发明申请

US20160165238A1 NEIGHBOR TILE BUFFERING FOR DEBLOCK FILTERING ACROSS TILE BOUNDARIES 审中-公开
标题翻译：相邻的边界缓冲区用于跨越边界的阻塞滤波
公开(公告)号：US20160165238A1
公开(公告)日：2016-06-09
申请号：US14564226
申请日：2014-12-09
申请人： ViXS Systems Inc.
发明人： Wendy Wai Yin Cheung , Xin Guo
IPC分类号： H04N19/176 , H04N19/86
CPC分类号： H04N19/86
摘要： Deblock filtering at the tile boundaries of a tiled picture use a tile neighbor buffer in addition to top neighbor buffer left neighbor buffers. The tile neighbor buffer buffers pixel data from the bottom right corner of the left-diagonal tile. When the top rows of pixels of a tile are being filtered, the top neighbor buffer stores the bottom rows of pixels of the tile above. As the tiles are processed in raster order, some of the pixels in the top neighbor buffer are the pixels in the bottom right corner of the left-diagonal tile of the next tile to be filtered. The portion of the top neighbor buffer storing pixel data representing this bottom right corner is copied directly from the top neighbor buffer to the tile neighbor buffer for further filtering when processing the next tile.
摘要翻译：在平铺图片的平铺边界处的去块过滤除了顶层邻居缓冲区左邻居缓冲区之外还使用平铺相邻缓冲区。瓦片相邻缓冲区缓冲左对角瓦片右下角的像素数据。当瓦片的顶部行的像素被过滤时，顶层相邻缓冲器存储上面的瓦片的最下面的像素行。当按照光栅顺序处理图块时，顶部相邻缓冲区中的一些像素是要过滤的下一个图块的左对齐图块的右下角的像素。存储表示右下角的像素数据的顶部相邻缓冲器的部分直接从顶部相邻缓冲器复制到平铺相邻缓冲器，用于在处理下一个图块时进一步过滤。

3. 发明申请

US20140205017A1 VIDEO PROCESSOR WITH REDUCED MEMORY BANDWIDTH AND METHODS FOR USE THEREWITH 有权
标题翻译：具有减少存储带宽的视频处理器及其使用方法
公开(公告)号：US20140205017A1
公开(公告)日：2014-07-24
申请号：US14133775
申请日：2013-12-19
申请人： ViXS Systems, Inc.
发明人： Xin Guo , Qi Yang , Edward Hong , Wendy Wai Yin Cheung , Eric Young , Chun-Chin Yeh
IPC分类号： H04N19/423 , H04N19/44
CPC分类号： H04N19/15 , G09G5/363 , G09G2360/127 , G09G2360/128 , H04N19/167 , H04N19/17 , H04N19/174 , H04N19/40 , H04N19/426 , H04N19/433
摘要： A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A tile engine includes a tile accumulation module that accumulates the uncompressed video frame data into a plurality of tile units, wherein each of the plurality of tile units includes a plurality of video span units. A tile compression/decompression module generates compressed video frame data for storage in a compressed video frame buffer by compressing the plurality of video span units into a plurality of compressed video span units and further that retrieves the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.
摘要翻译：视频处理装置包括视频处理单元，其基于未压缩的视频帧数据，根据视频压缩协议将视频输入信号解码为解码视频信号。瓦片引擎包括瓦片累积模块，其将未压缩视频帧数据累积成多个瓦片单元，其中多个瓦片单元中的每一个包括多个视频跨度单元。瓦片压缩/解压缩模块通过将多个视频跨度单元压缩成多个压缩视频范围单元并且还从压缩视频帧缓冲器中检索压缩视频帧数据来生成压缩视频帧数据以存储在压缩视频帧缓冲器中通过检索多个压缩视频范围单元并通过解压缩多个压缩视频跨度单元来生成未压缩的视频帧数据。

4. 发明申请

US20160134878A1 FRAME BUFFER COMPRESSION USING SEPARATE AGGREGATION OF FIXED-LENGTH AND VARIABLE-LENGTH COMPONENTS OF CODEWORDS 有权
标题翻译：使用固定长度和可变长度组件的分离式聚合框架缓冲器压缩
公开(公告)号：US20160134878A1
公开(公告)日：2016-05-12
申请号：US14536859
申请日：2014-11-10
申请人： ViXS Systems Inc.
发明人： Wendy Wai Yin Cheung , Xin Guo
IPC分类号： H04N19/184 , H04N19/169 , H04N19/172
CPC分类号： H04N19/91 , H03M7/4031 , H04N19/88
摘要： Each set of pels of an image frame is encoded into a corresponding set of codewords having fixed-length and unary variable-length components. The variable-length components are combined into a variable-length portion and the fixed-length components are separately combined into a fixed-length portion that is attached to the variable-length portion to complete a bit segment. For decompression, a first bit string of a fixed number of bits is identified as a fixed-length portion of the bit segment. A search window placed adjacent to the first bit string is scanned to find a second bit string having a number of termination bits equal to the number of codewords in the set, with the second bit string thus representing the variable-length portion of a corresponding bit segment. Each variable-length component of the identified variable-length portion is combined with a corresponding fixed-length component of the identified fixed-length portion to recreate a corresponding codeword.
摘要翻译：图像帧的每组像素被编码成具有固定长度和一元可变长度分量的相应的一组码字。可变长度分量被组合成可变长度部分，并且固定长度分量被分离地组合成固定长度部分，其连接到可变长度部分以完成位段。对于解压缩，固定位数的第一位串被识别为位段的固定长度部分。扫描与第一位串相邻放置的搜索窗口以找到具有等于集合中码字数量的终止位数的第二位串，其中第二位串因此表示相应位的可变长度部分分割。识别的可变长度部分的每个可变长度分量与所识别的固定长度部分的对应的固定长度分量组合以重新创建相应的码字。

5. 发明申请

US20140136855A1 SECURE KEY ACCESS WITH ONE-TIME PROGRAMMABLE MEMORY AND APPLICATIONS THEREOF 有权
标题翻译：具有一次性可编程存储器的安全密钥访问及其应用
公开(公告)号：US20140136855A1
公开(公告)日：2014-05-15
申请号：US14048391
申请日：2013-10-08
申请人： ViXS Systems, Inc.
发明人： Paul D. Ducharme , Wendy Wai Yin Cheung , Albert Yunsang Wong , Shijun Huang , Norman V.D. Stewart
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F21/602 , G06F21/6209 , G06F21/72 , G06F21/79 , G06F2221/2123 , G06F2221/2127 , H04L9/0822 , H04L9/088 , H04L9/0894 , H04L9/3247 , H04L2209/12 , H04L2209/60 , H04N21/4181 , H04N21/4183 , H04N21/42623 , H04N21/42692 , H04N21/4431 , H04N21/4435
摘要： A device includes a key store memory that stores one or more cryptographic keys. A rule set memory stores a set of rules for accessing the cryptographic keys. A key store arbitration module grants access to the cryptographic keys in accordance with the set of rules. The device can be used in conjunction with a key ladder. The device can include a one-time programmable memory and a load module that transfers the cryptographic keys from the one one-time programmable memory to the key store memory and the set of rules to the rule set memory. A validation module can validate the cryptographic keys and the set of rules stored in the key store and rule set memories, based on a signature defined by a signature rule.
摘要翻译：设备包括存储一个或多个加密密钥的密钥存储存储器。规则集存储器存储用于访问加密密钥的一组规则。密钥存储仲裁模块根据该组规则授予访问加密密钥的权限。该装置可以与一个梯子一起使用。该设备可以包括一次性可编程存储器和将密码密钥从一个一次性可编程存储器传送到密钥存储存储器的一个加载模块以及一组规则到规则集存储器。验证模块可以基于由签名规则定义的签名来验证存储在密钥存储器和规则集存储器中的加密密钥和规则集合。

6. 发明授权

US09407920B2 Video processor with reduced memory bandwidth and methods for use therewith 有权
标题翻译：具有减少的存储器带宽的视频处理器和与其一起使用的方法
公开(公告)号：US09407920B2
公开(公告)日：2016-08-02
申请号：US14133775
申请日：2013-12-19
申请人： ViXS Systems, Inc.
发明人： Xin Guo , Qi Yang , Edward Hong , Wendy Wai Yin Cheung , Eric Young , Chun-Chin Yeh
IPC分类号： G09G5/36 , H04N19/15 , H04N19/433 , H04N19/40 , H04N19/426 , H04N19/174 , H04N19/17 , H04N19/167
CPC分类号： H04N19/15 , G09G5/363 , G09G2360/127 , G09G2360/128 , H04N19/167 , H04N19/17 , H04N19/174 , H04N19/40 , H04N19/426 , H04N19/433
摘要： A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A tile engine includes a tile accumulation module that accumulates the uncompressed video frame data into a plurality of tile units, wherein each of the plurality of tile units includes a plurality of video span units. A tile compression/decompression module generates compressed video frame data for storage in a compressed video frame buffer by compressing the plurality of video span units into a plurality of compressed video span units and further that retrieves the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.
摘要翻译：视频处理装置包括视频处理单元，其基于未压缩的视频帧数据，根据视频压缩协议将视频输入信号解码为解码视频信号。瓦片引擎包括瓦片累积模块，其将未压缩视频帧数据累积成多个瓦片单元，其中多个瓦片单元中的每一个包括多个视频跨度单元。瓦片压缩/解压缩模块通过将多个视频跨度单元压缩成多个压缩视频范围单元并且还从压缩视频帧缓冲器中检索压缩视频帧数据来生成压缩视频帧数据以存储在压缩视频帧缓冲器中通过检索多个压缩视频范围单元并通过解压缩多个压缩视频跨度单元来生成未压缩视频帧数据。

7. 发明授权

US09317449B2 Secure key access with one-time programmable memory and applications thereof 有权
公开(公告)号：US09317449B2
公开(公告)日：2016-04-19
申请号：US14048391
申请日：2013-10-08
申请人： ViXS Systems, Inc.
发明人： Paul D. Ducharme , Wendy Wai Yin Cheung , Albert Yunsang Wong , Shijun Huang , Norman V. D. Stewart
IPC分类号： G06F12/14 , H04L9/08 , G06F21/60 , G06F21/62 , G06F21/72 , G06F21/79 , H04L9/32 , H04N7/167 , H04N21/418 , H04N21/426 , H04N21/443
CPC分类号： G06F12/1408 , G06F21/602 , G06F21/6209 , G06F21/72 , G06F21/79 , G06F2221/2123 , G06F2221/2127 , H04L9/0822 , H04L9/088 , H04L9/0894 , H04L9/3247 , H04L2209/12 , H04L2209/60 , H04N21/4181 , H04N21/4183 , H04N21/42623 , H04N21/42692 , H04N21/4431 , H04N21/4435
摘要： A device includes a key store memory that stores one or more cryptographic keys. A rule set memory stores a set of rules for accessing the cryptographic keys. A key store arbitration module grants access to the cryptographic keys in accordance with the set of rules. The device can be used in conjunction with a key ladder. The device can include a one-time programmable memory and a load module that transfers the cryptographic keys from the one one-time programmable memory to the key store memory and the set of rules to the rule set memory. A validation module can validate the cryptographic keys and the set of rules stored in the key store and rule set memories, based on a signature defined by a signature rule.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式