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1. 发明申请

US20140075158A1 IDENTIFYING LOAD-HIT-STORE CONFLICTS 有权
公开(公告)号：US20140075158A1
公开(公告)日：2014-03-13
申请号：US13611006
申请日：2012-09-12
申请人： Venkat R. Indukuru , Alexander E. Mericas , Satish K. Sadasivam , Madhavi G. Valluri
发明人： Venkat R. Indukuru , Alexander E. Mericas , Satish K. Sadasivam , Madhavi G. Valluri
IPC分类号： G06F9/312
CPC分类号： G06F9/44552 , G06F9/3834
摘要： A computing device identifies a load instruction and store instruction pair that causes a load-hit-store conflict. A processor tags a first load instruction that instructs the processor to load a first data set from memory. The processor stores an address at which the first load instruction is located in memory in a special purpose register. The processor determines where the first load instruction has a load-hit-store conflict with a first store instruction. If the processor determines the first load instruction has a load-hit store conflict with the first store instruction, the processor stores an address at which the first data set is located in memory in a second special purpose register, tags the first data set being stored by the first store instruction, stores an address at which the first store instruction is located in memory in a third special purpose register and increases a conflict counter.

2. 发明授权

US09229745B2 Identifying load-hit-store conflicts 有权
标题翻译：识别加载命中商店冲突
公开(公告)号：US09229745B2
公开(公告)日：2016-01-05
申请号：US13611006
申请日：2012-09-12
申请人： Venkat R. Indukuru , Alexander E. Mericas , Satish K. Sadasivam , Madhavi G. Valluri
发明人： Venkat R. Indukuru , Alexander E. Mericas , Satish K. Sadasivam , Madhavi G. Valluri
IPC分类号： G06F9/00 , G06F9/445 , G06F9/38
CPC分类号： G06F9/44552 , G06F9/3834
摘要： A computing device identifies a load instruction and store instruction pair that causes a load-hit-store conflict. A processor tags a first load instruction that instructs the processor to load a first data set from memory. The processor stores an address at which the first load instruction is located in memory in a special purpose register. The processor determines where the first load instruction has a load-hit-store conflict with a first store instruction. If the processor determines the first load instruction has a load-hit store conflict with the first store instruction, the processor stores an address at which the first data set is located in memory in a second special purpose register, tags the first data set being stored by the first store instruction, stores an address at which the first store instruction is located in memory in a third special purpose register and increases a conflict counter.
摘要翻译：计算设备识别导致加载命中 - 存储冲突的加载指令和存储指令对。处理器标记指示处理器从存储器加载第一数据集的第一加载指令。处理器将特定目的寄存器中的第一加载指令所在的地址存储在存储器中。处理器确定第一个加载指令与第一个存储指令的加载命中 - 存储冲突的位置。如果处理器确定第一加载指令具有与第一存储指令的加载命中存储冲突，则处理器将第一数据集所在的地址存储在第二专用寄存器中的存储器中，对存储的第一数据集进行标记通过第一存储指令，将第一存储指令所在的地址存储在第三专用寄存器中，并增加冲突计数器。

3. 发明申请

US20120278594A1 PERFORMANCE BOTTLENECK IDENTIFICATION TOOL 有权
标题翻译：性能BOTTLENECK识别工具
公开(公告)号：US20120278594A1
公开(公告)日：2012-11-01
申请号：US13095792
申请日：2011-04-27
申请人： Prathiba Kumar , Rajan Ravindran , Satish K. Sadasivam , Madhavi G. Valluri
发明人： Prathiba Kumar , Rajan Ravindran , Satish K. Sadasivam , Madhavi G. Valluri
IPC分类号： G06F9/30
CPC分类号： G06F11/3612 , G06F11/3409 , G06F11/3476 , G06F2201/865 , G06F2201/88
摘要： A computer program product for identifying bottlenecks includes a computer readable storage medium with stored computer readable program instructions. The computer readable program instructions, when executed, provide a data collector module, a mapper module, and an analyzer module that are collectively configured to read mapped data and configuration files, and identify, based upon the mapped data and the configuration files, an undesirable bottleneck condition that causes a computer program to run inefficiently. A method includes reading a configuration file that includes data regarding processor components, and collecting data from hardware activity counters based upon the configuration file. The method also includes mapping the collected data to corresponding sections of code of a computer program, reading the mapped data and the configuration file, and identifying, based upon the reading of the mapped data and the configuration file, an undesirable bottleneck condition that causes the processor to run the computer program inefficiently.
摘要翻译：用于识别瓶颈的计算机程序产品包括具有存储的计算机可读程序指令的计算机可读存储介质。计算机可读程序指令在执行时提供数据收集器模块，映射器模块和分析器模块，其被共同配置为读取映射的数据和配置文件，并且基于映射的数据和配置文件来识别不期望的导致计算机程序运行效率低下的瓶颈条件。一种方法包括读取包括关于处理器组件的数据的配置文件，以及基于配置文件从硬件活动计数器收集数据。该方法还包括将收集的数据映射到计算机程序的相应代码段，读取映射数据和配置文件，以及基于映射数据和配置文件的读取来识别不期望的瓶颈条件，处理器无效率地运行计算机程序。

4. 发明授权

US09032375B2 Performance bottleneck identification tool 有权
标题翻译：性能瓶颈识别工具
公开(公告)号：US09032375B2
公开(公告)日：2015-05-12
申请号：US13095792
申请日：2011-04-27
申请人： Prathiba Kumar , Rajan Ravindran , Satish K. Sadasivam , Madhavi G. Valluri
发明人： Prathiba Kumar , Rajan Ravindran , Satish K. Sadasivam , Madhavi G. Valluri
IPC分类号： G06F9/30 , G06F11/36 , G06F11/34
CPC分类号： G06F11/3612 , G06F11/3409 , G06F11/3476 , G06F2201/865 , G06F2201/88
摘要： A computer program product for identifying bottlenecks includes a computer readable storage medium with stored computer readable program instructions. The computer readable program instructions, when executed, provide a data collector module, a mapper module, and an analyzer module that are collectively configured to read mapped data and configuration files, and identify, based upon the mapped data and the configuration files, an undesirable bottleneck condition that causes a computer program to run inefficiently. A method includes reading a configuration file that includes data regarding processor components, and collecting data from hardware activity counters based upon the configuration file. The method also includes mapping the collected data to corresponding sections of code of a computer program, reading the mapped data and the configuration file, and identifying, based upon the reading of the mapped data and the configuration file, an undesirable bottleneck condition that causes the processor to run the computer program inefficiently.
摘要翻译：用于识别瓶颈的计算机程序产品包括具有存储的计算机可读程序指令的计算机可读存储介质。计算机可读程序指令在执行时提供数据收集器模块，映射器模块和分析器模块，其被共同配置为读取映射的数据和配置文件，并且基于映射的数据和配置文件来识别不期望的导致计算机程序运行效率低下的瓶颈条件。一种方法包括读取包括关于处理器组件的数据的配置文件，以及基于配置文件从硬件活动计数器收集数据。该方法还包括将收集的数据映射到计算机程序的相应代码段，读取映射数据和配置文件，以及基于映射数据和配置文件的读取来识别不期望的瓶颈条件，处理器无效率地运行计算机程序。

5. 发明授权

US09129057B2 Smart multiplexing of performance counters for performance measurement 有权
标题翻译：用于性能测量的性能计数器的智能复用
公开(公告)号：US09129057B2
公开(公告)日：2015-09-08
申请号：US13461059
申请日：2012-05-01
申请人： Satish K. Sadasivam , Prathiba Kumar , Rajan Ravindran , Sangram Alapati
发明人： Satish K. Sadasivam , Prathiba Kumar , Rajan Ravindran , Sangram Alapati
IPC分类号： G06F15/00 , G01C17/00 , G06F11/34
CPC分类号： G06F11/3466 , G06F2201/81 , G06F2201/86 , G06F2201/865 , G06F2201/88
摘要： The present disclosure includes, but is not limited to, a method, system and computer-usable medium for improving performance measurement by analyzing the various events in a multiplexing counting mode and configuring the sampling time accordingly to more effectively performing the sampling. In certain embodiments, when groups of operations are identified for sampling, the present disclosure generates a time sampling table for these groups of operations. The time sampling table is dynamically altered during the runtime of the application to alter the sampling interval of each group. The sampling interval of each group can be increased or decreased based on a threshold of occurrence of the event. This disclosure provides more accurate performance measurement of important events and facilitates a determination of how important events impact application performance.
摘要翻译：本公开包括但不限于用于通过分析多路复用计数模式中的各种事件并相应地配置采样时间来更有效地执行采样来改善性能测量的方法，系统和计算机可用介质。在某些实施例中，当识别用于采样的组操作时，本公开为这些操作组生成时间采样表。时间采样表在应用程序的运行时间内被动态地改变，以改变每个组的采样间隔。可以根据事件发生的阈值来增加或减少每个组的采样间隔。本公开提供了对重要事件的更准确的性能测量，并且有助于确定事件如何影响应用程序性能。

6. 发明授权

US08904208B2 Run-time task-level dynamic energy management 有权
标题翻译：运行时任务级动态能量管理
公开(公告)号：US08904208B2
公开(公告)日：2014-12-02
申请号：US13289415
申请日：2011-11-04
申请人： Sangram Alapati , Amit Dugar , Prathiba Kumar , Satish K. Sadasivam
发明人： Sangram Alapati , Amit Dugar , Prathiba Kumar , Satish K. Sadasivam
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3296 , G06F1/324 , G06F1/329 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.
摘要翻译：提供了运行时任务级动态能量管理的机制。响应于被标记为能量管理的应用，将应用的第一指令的指令地址映射到应用中的应用代码的一部分。对应用程序代码的部分进行硬件资源活动的监视。然后基于滴答指示器，资源活动和强度指示符的值，对应用代码的一部分实现能量管理的级别。

7. 发明申请

US20130297258A1 Smart Multiplexing of Performance Counters for Performance Measurement 有权
标题翻译：用于性能测量的性能计数器的智能复用
公开(公告)号：US20130297258A1
公开(公告)日：2013-11-07
申请号：US13461059
申请日：2012-05-01
申请人： Satish K. Sadasivam , Prathiba Kumar , Rajan Ravindran , Sangram Alapati
发明人： Satish K. Sadasivam , Prathiba Kumar , Rajan Ravindran , Sangram Alapati
IPC分类号： G06F15/00
CPC分类号： G06F11/3466 , G06F2201/81 , G06F2201/86 , G06F2201/865 , G06F2201/88
摘要： The present disclosure includes, but is not limited to, a method, system and computer-usable medium for improving performance measurement by analyzing the various events in a multiplexing counting mode and configuring the sampling time accordingly to more effectively performing the sampling. In certain embodiments, when groups of operations are identified for sampling, the present disclosure generates a time sampling table for these groups of operations. The time sampling table is dynamically altered during the runtime of the application to alter the sampling interval of each group. The sampling interval of each group can be increased or decreased based on a threshold of occurrence of the event. This disclosure provides more accurate performance measurement of important events and facilitates a determination of how important events impact application performance.
摘要翻译：本公开包括但不限于用于通过分析多路复用计数模式中的各种事件并相应地配置采样时间来更有效地执行采样来改善性能测量的方法，系统和计算机可用介质。在某些实施例中，当识别用于采样的组操作时，本公开为这些操作组生成时间采样表。时间采样表在应用程序的运行时间内被动态地改变，以改变每个组的采样间隔。可以根据事件发生的阈值来增加或减少每个组的采样间隔。本公开提供了对重要事件的更准确的性能测量，并且有助于确定事件如何影响应用程序性能。

8. 发明申请

US20130117588A1 Run-Time Task-Level Dynamic Energy Management 有权
标题翻译：运行时任务级动态能量管理
公开(公告)号：US20130117588A1
公开(公告)日：2013-05-09
申请号：US13289415
申请日：2011-11-04
申请人： Sangram Alapati , Amit Dugar , Prathiba Kumar , Satish K. Sadasivam
发明人： Sangram Alapati , Amit Dugar , Prathiba Kumar , Satish K. Sadasivam
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3296 , G06F1/324 , G06F1/329 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.
摘要翻译：提供了运行时任务级动态能量管理的机制。响应于被标记为能量管理的应用，将应用的第一指令的指令地址映射到应用中的应用代码的一部分。对应用程序代码的部分进行硬件资源活动的监视。然后基于滴答指示器，资源活动和强度指示符的值，对应用代码的一部分实现能量管理的级别。

9. 发明授权

US08850266B2 Effective validation of execution units within a processor 有权
公开(公告)号：US08850266B2
公开(公告)日：2014-09-30
申请号：US13159564
申请日：2011-06-14
申请人： Sangram Alapati , Prathiba Kumar , Varun Mallikarjunan , Satish K. Sadasivam
发明人： Sangram Alapati , Prathiba Kumar , Varun Mallikarjunan , Satish K. Sadasivam
IPC分类号： G06F11/00 , G06F11/22 , G06F11/263
CPC分类号： G06F11/263 , G06F11/2236
摘要： A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.

10. 发明申请

US20120324208A1 Effective Validation of Execution Units Within a Processor 有权
标题翻译：处理器内执行单元的有效验证
公开(公告)号：US20120324208A1
公开(公告)日：2012-12-20
申请号：US13159564
申请日：2011-06-14
申请人： Sangram Alapati , Prathiba Kumar , Varun Mallikarjunan , Satish K. Sadasivam
发明人： Sangram Alapati , Prathiba Kumar , Varun Mallikarjunan , Satish K. Sadasivam
IPC分类号： G06F9/30
CPC分类号： G06F11/263 , G06F11/2236
摘要： A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.
摘要翻译：提供了一种用于有效验证处理器内的执行单元的机制。生成分支测试模式，由执行单元进行验证测试。从一组执行模式中选择执行模式，从而形成所选择的执行模式。所选择的执行模式被加载到条件寄存器中。分支测试模式由执行单元基于条件寄存器中所选择的执行模式执行。响应于分支测试模式结束，在执行分支测试模式期间从执行单元输出的值与一组预期结果进行比较。响应于比较的匹配，对于该组执行模式中的每个执行模式重复该过程。响应于执行模式集合中的执行模式的比较的匹配，执行单元被验证。

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