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1. 发明申请

US20080170598A1 Cascaded injection resonator for coherent beam combining of laser arrays 失效
公开(公告)号：US20080170598A1
公开(公告)日：2008-07-17
申请号：US11652238
申请日：2007-01-11
申请人： Vassili Kireev , Yun Liu , Vladimir Protopopescu , Yehuda Braiman
发明人： Vassili Kireev , Yun Liu , Vladimir Protopopescu , Yehuda Braiman
IPC分类号： H01S5/00 , H01S3/08
CPC分类号： H01S5/4062 , H01S3/10092 , H01S5/4006 , H01S5/4068 , H01S5/4081
摘要： The invention provides a cascaded injection resonator for coherent beam combining of laser arrays. The resonator comprises a plurality of laser emitters arranged along at least one plane and a beam sampler for reflecting at least a portion of each laser beam that impinges on the beam sampler, the portion of each laser beam from one of the laser emitters being reflected back to another one of the laser emitters to cause a beam to be generated from the other one of the laser emitters to the beam reflector. The beam sampler also transmits a portion of each laser beam to produce a laser output beam such that a plurality of laser output beams of the same frequency are produced. An injection laser beam is directed to a first laser emitter to begin a process of generating and reflecting a laser beam from one laser emitter to another laser emitter in the plurality. A method of practicing the invention is also disclosed.

2. 发明授权

US07440483B2 Cascaded injection resonator for coherent beam combining of laser arrays 失效
标题翻译：用于激光阵列的相干光束组合的级联注入谐振器
公开(公告)号：US07440483B2
公开(公告)日：2008-10-21
申请号：US11652238
申请日：2007-01-11
申请人： Vassili Kireev , Yun Liu , Vladimir Protopopescu , Yehuda Braiman
发明人： Vassili Kireev , Yun Liu , Vladimir Protopopescu , Yehuda Braiman
IPC分类号： H01S5/00
CPC分类号： H01S5/4062 , H01S3/10092 , H01S5/4006 , H01S5/4068 , H01S5/4081
摘要： The invention provides a cascaded injection resonator for coherent beam combining of laser arrays. The resonator comprises a plurality of laser emitters arranged along at least one plane and a beam sampler for reflecting at least a portion of each laser beam that impinges on the beam sampler, the portion of each laser beam from one of the laser emitters being reflected back to another one of the laser emitters to cause a beam to be generated from the other one of the laser emitters to the beam reflector. The beam sampler also transmits a portion of each laser beam to produce a laser output beam such that a plurality of laser output beams of the same frequency are produced. An injection laser beam is directed to a first laser emitter to begin a process of generating and reflecting a laser beam from one laser emitter to another laser emitter in the plurality. A method of practicing the invention is also disclosed.
摘要翻译：本发明提供了用于激光阵列的相干光束组合的级联注入谐振器。谐振器包括沿着至少一个平面布置的多个激光发射器和用于反射撞击在光束采样器上的每个激光束的至少一部分的光束采样器，来自激光发射器之一的每个激光束的部分被反射回到另一个激光发射器，以使光束从另一个激光发射器产生到光束反射器。光束采样器还传输每个激光束的一部分以产生激光输出光束，使得产生相同频率的多个激光输出光束。注入激光束被引导到第一激光发射器以开始产生并将来自一个激光发射器的激光束反射到多个激光发射器的处理。还公开了实施本发明的方法。

3. 发明授权

US09853666B1 Adaptive analog parallel combiner 有权
公开(公告)号：US09853666B1
公开(公告)日：2017-12-26
申请号：US15345239
申请日：2016-11-07
申请人： Albert Vareljian , Vassili Kireev
发明人： Albert Vareljian , Vassili Kireev
IPC分类号： H04L27/06 , H04B1/10 , H04B1/16 , H03G3/20
CPC分类号： H03G5/005 , H03G5/16 , H03H15/00 , H03H15/023 , H03H17/00
摘要： An adaptive analog parallel combiner circuit for receiver data recovery from a communication signal is provided. The circuit includes a summer that sums outputs of a plurality of filter taps in parallel, including zeroth and first through Nth filter taps, each filter tap having as input the communication signal or a version thereof, wherein N is a finite integer greater than or equal to two. The zeroth filter tap has an amplifier with gain controlled by a zeroth adaptive gain control coefficient, and each of the first through Nth filter taps having an all pass filter and gain controlled amplification, with gain controlled by a corresponding one of a first through Nth adaptive gain control coefficients and the all pass filter implementing a transfer function having a zero and a pole equaling each other and at a base frequency divided by a corresponding integer from one through N.

4. 发明授权

US09406738B2 Inductive structure formed using through silicon vias 有权
标题翻译：使用硅通孔形成的感应结构
公开(公告)号：US09406738B2
公开(公告)日：2016-08-02
申请号：US13187234
申请日：2011-07-20
申请人： Vassili Kireev , James Karp
发明人： Vassili Kireev , James Karp
IPC分类号： H01L23/48 , H01L25/16 , H01L27/08 , H01L49/02 , H01L23/14 , H01L23/498 , H01L23/522 , H01L23/64 , H01L25/065 , H01L23/00
CPC分类号： H01L28/10 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L23/5227 , H01L23/645 , H01L24/16 , H01L25/0652 , H01L25/0655 , H01L25/16 , H01L2224/131 , H01L2224/16235 , H01L2924/15192 , H01L2924/15311 , H01L2924/014
摘要： An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV.
摘要翻译：用于集成电路的电感器可以包括第一匝，其包括耦合到第二TSV的第一至第矽通孔（TSV）。电感器可以包括耦合到第二TSV的第三TSV。

5. 发明授权

US08823133B2 Interposer having an inductor 有权
标题翻译：具有电感的插入器
公开(公告)号：US08823133B2
公开(公告)日：2014-09-02
申请号：US13075059
申请日：2011-03-29
申请人： Michael O. Jenkins , James Karp , Vassili Kireev , Ephrem C. Wu
发明人： Michael O. Jenkins , James Karp , Vassili Kireev , Ephrem C. Wu
IPC分类号： H01L27/08 , H01L25/18 , H01L23/60 , H01L23/64 , H01L23/498 , H01L25/065
CPC分类号： H01L23/645 , H01L23/49822 , H01L23/60 , H01L23/642 , H01L25/0655 , H01L25/18 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01019 , H01L2924/15192 , H01L2924/15311 , H01L2224/0401
摘要： An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.
摘要翻译：公开了一种多芯片模块的实施例。对于多芯片模块的该实施例，包括半导体管芯和插入件。插入器具有导电层，电介质层和衬底。内部互连结构将半导体管芯耦合到插入器。外部互连结构用于将插入器耦合到外部设备。第一电感器包括插入器的一个或多个导电层的至少一部分。第一电感器的第一端耦合到内部互连结构的内部互连结构。第一电感器的第二端耦合到外部互连结构的外部互连结构。

6. 发明授权

US08559145B1 Serializer/deserializer frontend 有权
标题翻译：串行器/解串器前端
公开(公告)号：US08559145B1
公开(公告)日：2013-10-15
申请号：US13332678
申请日：2011-12-21
申请人： Vassili Kireev , Jafar Savoj
发明人： Vassili Kireev , Jafar Savoj
IPC分类号： H02H3/22
CPC分类号： G06F13/385 , H02H9/046
摘要： A receiver frontend includes a first input junction for receiving a first input signal, a second input junction for receiving a second input signal, a first output junction, a second output junction, and circuitry configured to perform equalization on the first input signal and the second input signal to establish a first output signal with a desired frequency response at the first output junction, and to establish a second output signal with a desired frequency response at the second output junction, and perform common-mode voltage adjustment on a common-mode voltage associated with the first output signal and the second output signal.
摘要翻译：接收器前端包括用于接收第一输入信号的第一输入端，用于接收第二输入信号的第二输入端，第一输出结，第二输出结和被配置为对第一输入信号执行均衡的电路，输入信号以在第一输出结处建立具有期望频率响应的第一输出信号，并且在第二输出结处建立具有期望频率响应的第二输出信号，并且在共模电压上执行共模电压调节与第一输出信号和第二输出信号相关联。

7. 发明申请

US20110248811A1 STACKED DUAL INDUCTOR STRUCTURE 有权
标题翻译：堆叠式双电感结构
公开(公告)号：US20110248811A1
公开(公告)日：2011-10-13
申请号：US12755781
申请日：2010-04-07
申请人： Vassili Kireev
发明人： Vassili Kireev
IPC分类号： H01F5/00
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The dual inductor structure can include a first inductor including a first plurality of coils. Each coil of the first plurality of coils can be disposed within a different one of a plurality of conductive layers. The coils of the first plurality of coils can be vertically stacked and concentric to a vertical axis. The dual inductor structure further can include a second inductor including a second plurality of coils. Each of the second plurality of coils can be disposed within a different one of the plurality of conductive layers. The coils of the second plurality of coils can be vertically stacked and concentric to the vertical axis. Within each conductive layer, a coil of the second plurality of coils can be disposed within an inner perimeter of a coil of the first plurality of coils.
摘要翻译：双电感器结构可以包括包括第一多个线圈的第一电感器。第一多个线圈的每个线圈可以设置在多个导电层中的不同的一个中。第一组线圈的线圈可垂直地堆叠并与垂直轴同心。双电感结构还可以包括包括第二多个线圈的第二电感器。第二多个线圈中的每一个可以设置在多个导电层中的不同的一个中。第二组线圈的线圈可垂直地堆叠并与垂直轴同心。在每个导电层内，第二多个线圈的线圈可以设置在第一多个线圈的线圈的内周边内。

8. 发明授权

US11057065B1 Adaptive analog parallel combiner 有权
公开(公告)号：US11057065B1
公开(公告)日：2021-07-06
申请号：US16410545
申请日：2019-05-13
申请人： Albert Vareljian , Vassili Kireev
发明人： Albert Vareljian , Vassili Kireev
IPC分类号： H04L27/08 , H04B1/10 , H04B1/16 , H03G3/20 , H03G5/16 , H03G5/00 , H03H17/00 , H03H15/00
摘要： An adaptive analog parallel combiner circuit for receiver data recovery from a communication signal is provided. The circuit includes a summer that sums outputs of a plurality of filter taps in parallel, including zeroth and first through Nth filter taps, each filter tap having as input the communication signal or a version thereof, wherein N is a finite integer greater than or equal to two. The zeroth filter tap has an amplifier with gain controlled by a zeroth adaptive gain control coefficient, and each of the first through Nth filter taps having an all pass filter and gain controlled amplification, with gain controlled by a corresponding one of a first through Nth adaptive gain control coefficients and the all pass filter implementing a transfer function having a zero and a pole equaling each other and at a base frequency divided by a corresponding integer from one through N.

9. 发明授权

US08686539B1 Inductor having a deep-well noise isolation shield 有权
标题翻译：具有深井噪声隔离屏蔽的电感器
公开(公告)号：US08686539B1
公开(公告)日：2014-04-01
申请号：US12906026
申请日：2010-10-15
申请人： Vassili Kireev , Parag Upadhyaya , Toan D. Tran
发明人： Vassili Kireev , Parag Upadhyaya , Toan D. Tran
IPC分类号： H01L27/08
CPC分类号： H01L27/08 , H01L23/5225 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A shielded inductor in an integrated circuit includes conductive loops disposed on a deep-well noise shield for isolating a noise coupling between the conductive loops and the substrate of the integrated circuit. The deep-well noise shield includes a first well disposed within a second well that is disposed within the substrate of the integrated circuit. The second well includes a peripheral well, a deep-well layer, and slot wells. The peripheral well surrounds a periphery of the first well. The peripheral well and the deep-well layer are coupled together to provide two p-n junctions that separate the first well and the substrate. The slot wells are distributed inside the periphery of the first well. Each slot well and the deep-well layer are coupled together. Each slot well has a width and a length that is at least three times the width.
摘要翻译：集成电路中的屏蔽电感器包括设置在深井噪声屏蔽上的导电回路，用于隔离导电回路与集成电路的基板之间的噪声耦合。深井噪声屏蔽包括设置在集成电路的基板内的第二阱内的第一阱。第二井包括外围井，深井层和槽井。外围井围绕第一井的周边。外围阱和深阱层耦合在一起以提供分离第一阱和衬底的两个p-n结。槽井分布在第一井的周边内。每个槽槽和深井层耦合在一起。每个狭槽的宽度和长度至少为宽度的三倍。

10. 发明授权

US08358192B2 Multiple-loop symmetrical inductor 有权
标题翻译：多回路对称电感
公开(公告)号：US08358192B2
公开(公告)日：2013-01-22
申请号：US13463497
申请日：2012-05-03
申请人： Vassili Kireev , Parag Upadhyaya , Mark J. Marlett
发明人： Vassili Kireev , Parag Upadhyaya , Mark J. Marlett
IPC分类号： H01F27/29 , H01F5/00 , H01F27/28 , H01F7/06
CPC分类号： H01F17/0013 , H01F2017/0073 , Y10T29/4902
摘要： A symmetrical inductor includes an integrated circuit having a plurality of conductive layers. A first loop is disposed in an upper layer of the conductive layers, and at least two strapped loops are disposed in at least two layers of the conductive layers, respectively. The strapped loops are coupled in series to the first loop, and the at least two layers are below the upper layer. A second loop is disposed in the upper layer and is coupled in series to the at least two strapped loops. A first terminal electrode is coupled to the first loop, and a second terminal electrode is coupled to the second loop. A center-tap electrode is coupled to the at least two strapped loops.
摘要翻译：对称电感器包括具有多个导电层的集成电路。第一环设置在导电层的上层中，并且至少两个绑扎环分别设置在至少两层导电层中。捆扎环与第一环串联耦合，并且至少两层位于上层下方。第二环设置在上层中并串联耦合到至少两个带状环。第一端子电极耦合到第一环路，并且第二端子电极耦合到第二环路。中心抽头电极耦合到至少两个绑扎环。

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