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1. 发明授权

US09085461B2 Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis 有权
标题翻译：使用电化学合成在图案化晶片上制造聚合物阵列的方法和装置
公开(公告)号：US09085461B2
公开(公告)日：2015-07-21
申请号：US13473338
申请日：2012-05-16
申请人： Valery M. Dubin , Florian Gstrein , Gordon D. Holt , Brandon Barnett
发明人： Valery M. Dubin , Florian Gstrein , Gordon D. Holt , Brandon Barnett
IPC分类号： H01L21/00 , B82Y30/00 , B01J19/00
CPC分类号： B82Y30/00 , B01J19/0046 , B01J2219/00497 , B01J2219/005 , B01J2219/00527 , B01J2219/00574 , B01J2219/00576 , B01J2219/00585 , B01J2219/00596 , B01J2219/00653 , B01J2219/00659 , B01J2219/00662 , B01J2219/00675 , B01J2219/00677 , B01J2219/00689 , B01J2219/00713 , B01J2219/00722 , B01J2219/00725
摘要： A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
摘要翻译：具有在晶片上具有多个管芯（也称为阵列芯片）的晶片，该管芯具有产生脱保护试剂的电极，用于电化学合成材料的工作电极，邻近工作电极的约束电极以限制反应性试剂，以及管芯焊盘，其中，所述多个管芯的管芯焊盘在晶片上互连，以在多个工作电极上并行地电化学地合成所述材料。另外，公开了一种用于晶片尺寸制造多个管芯的方法和用于在晶片上的多个管芯上并行地电化学合成材料的方法。

2. 发明授权

US08541876B2 Microelectronic package having direct contact heat spreader and method of manufacturing same 有权
标题翻译：具有直接接触式散热器的微电子封装及其制造方法
公开(公告)号：US08541876B2
公开(公告)日：2013-09-24
申请号：US11242176
申请日：2005-09-30
申请人： Daoqiang Lu , Chuan Hu , Gilroy J. Vandentop , Shriram Ramanathan , Rajashree Baskaran , Valery M. Dubin
发明人： Daoqiang Lu , Chuan Hu , Gilroy J. Vandentop , Shriram Ramanathan , Rajashree Baskaran , Valery M. Dubin
IPC分类号： H01L23/10
CPC分类号： H01L24/83 , H01L21/4871 , H01L23/3735 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/83 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/18161 , H01L2924/19106 , H01L2924/00
摘要： A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.
摘要翻译：一种制造具有直接接触散热器的微电子封装的方法，根据该方法形成的封装，根据该方法形成的模具散热器组合以及包含封装的系统。该方法包括金属化微电子管芯的背面以形成直接接触并固定到管芯背面的散热器主体，从而产生模具散热器组合。该封装包括模具散热器组合和与模具结合的衬底。

3. 发明授权

US08053774B2 Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis 有权
标题翻译：使用电化学合成在图案化晶片上制造聚合物阵列的方法和装置
公开(公告)号：US08053774B2
公开(公告)日：2011-11-08
申请号：US11144679
申请日：2005-06-06
申请人： Valery M. Dubin , Florian Gstrein , Gordon D. Holt , Brandon Barnett
发明人： Valery M. Dubin , Florian Gstrein , Gordon D. Holt , Brandon Barnett
IPC分类号： H01L23/58
CPC分类号： B82Y30/00 , B01J19/0046 , B01J2219/00497 , B01J2219/005 , B01J2219/00527 , B01J2219/00574 , B01J2219/00576 , B01J2219/00585 , B01J2219/00596 , B01J2219/00653 , B01J2219/00659 , B01J2219/00662 , B01J2219/00675 , B01J2219/00677 , B01J2219/00689 , B01J2219/00713 , B01J2219/00722 , B01J2219/00725
摘要： A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
摘要翻译：具有在晶片上具有多个管芯（也称为阵列芯片）的晶片，该管芯具有产生脱保护试剂的电极，用于电化学合成材料的工作电极，邻近工作电极的约束电极以限制反应性试剂，以及管芯焊盘，其中，所述多个管芯的管芯焊盘在晶片上互连，以在多个工作电极上并行地电化学地合成所述材料。另外，公开了一种用于晶片尺寸制造多个管芯的方法和用于在晶片上的多个管芯上并行地电化学合成材料的方法。

4. 发明授权

US07709873B2 Polymer memory with adhesion layer containing an immobilized metal 有权
标题翻译：含有固定金属的粘合层的聚合物记忆
公开(公告)号：US07709873B2
公开(公告)日：2010-05-04
申请号：US11096389
申请日：2005-03-31
申请人： Valery M. Dubin , Ebrahim Andideh
发明人： Valery M. Dubin , Ebrahim Andideh
IPC分类号： H01L29/76 , H01L29/74 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10 , B82Y10/00 , B82Y30/00 , H01L29/516 , H01L29/78391 , Y10T29/435
摘要： An embodiment mitigates one or more of the limiting factors of fabricating polymer ferroelectric memory devices. For example, an embodiment reduces the degradation of the ferroelectric polymer due to the polymer's reaction with, and migration or diffusion of, adjacent metal electrode material. Further, the ferroelectric polymer is exposed to fewer potentially high temperature or high energy processes that may damage the polymer. An embodiment further incorporates an immobilized catalyst to improve the adhesion between adjacent layers, and particularly between the electrolessly plated electrodes and the ferroelectric polymer.
摘要翻译：一个实施例减轻了制造聚合物铁电存储器件的一个或多个限制因素。例如，一个实施方案由于聚合物与相邻的金属电极材料的反应和迁移或扩散而降低了铁电聚合物的劣化。此外，铁电聚合物暴露于可能损坏聚合物的较少的潜在高温或高能量过程。一个实施方案还包括固定化的催化剂以改善相邻层之间的粘合性，特别是在无电镀电极和铁电聚合物之间。

5. 发明申请

US20100022083A1 CARBON NANOTUBE INTERCONNECT STRUCTURES 审中-公开
标题翻译：碳纳米管互连结构
公开(公告)号：US20100022083A1
公开(公告)日：2010-01-28
申请号：US12548779
申请日：2009-08-27
申请人： Florian Gstrein , Valery M. Dubin , Juan E. Dominguez , Adrien R. Lavoie
发明人： Florian Gstrein , Valery M. Dubin , Juan E. Dominguez , Adrien R. Lavoie
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/76838 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/75 , H01L2924/00
摘要： A method including forming an interconnect of single-walled carbon nanotubes on a sacrificial substrate; transferring the interconnect from the sacrificial substrate to a circuit substrate; and coupling the interconnect to a contact point on the circuit substrate. A method including forming a nanotube bundle on a circuit substrate between a first contact point and a second contact point, the nanotube defining a lumen therethrough; filling a portion of a length of the lumen of the nanotube bundle with an electrically conductive material; and coupling the electrically conductive material to the second contact point. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor including a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures including carbon nanotube bundles.
摘要翻译：一种包括在牺牲衬底上形成单层碳纳米管的互连的方法; 将所述互连件从所述牺牲衬底转移到电路衬底; 以及将所述互连件耦合到所述电路基板上的接触点。一种方法，包括在第一接触点和第二接触点之间的电路基板上形成纳米管束，所述纳米管限定通过其的腔; 用导电材料填充纳米管束管腔长度的一部分; 以及将所述导电材料耦合到所述第二接触点。一种包括计算设备的系统，包括微处理器，微处理器耦合到印刷电路板，微处理器包括具有多个电路器件的衬底，该电路器件具有通过包括碳纳米管束的互连结构与多个电路器件形成的电连接。

6. 发明申请

US20080296768A1 Copper nucleation in interconnects having ruthenium layers 审中-公开
标题翻译：具有钌层的互连中的铜成核
公开(公告)号：US20080296768A1
公开(公告)日：2008-12-04
申请号：US11639636
申请日：2006-12-14
申请人： Ramanan V. Chebiam , Valery M. Dubin
发明人： Ramanan V. Chebiam , Valery M. Dubin
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L21/76873 , H01L21/76846 , H01L21/76864 , H01L2221/1089
摘要： A method for fabrication a metal interconnect that includes a ruthenium layer and minimizes void formation comprises forming a barrier layer on a substrate having a trench, depositing a ruthenium layer on the barrier layer, depositing an alloy-seed layer on the ruthenium layer, using an electroless plating process to deposit a copper seed layer on the alloy-seed layer, and using an electroplating process to deposit a bulk metal layer on the copper seed layer. The alloy-seed layer inhibits void formation issues at the ruthenium-copper interface and improves electromigration issues. The electroless copper seed layer inhibits the alloy-seed layer from dissolving into the electroplating bath and reduces electrical resistance across the substrate during the electroplating process.
摘要翻译：一种用于制造包括钌层并且使空隙形成最小化的金属互连的方法包括在具有沟槽的衬底上形成阻挡层，在阻挡层上沉积钌层，在钌层上沉积合金种子层，使用化学镀处理以在合金种子层上沉积铜籽晶层，并使用电镀工艺在铜籽晶层上沉积体金属层。合金种子层抑制钌 - 铜界面处的空隙形成问题，并改善电迁移问题。化学镀铜种子层抑制合金种子层溶解到电镀浴中，并且在电镀过程期间降低跨衬底的电阻。

7. 发明申请

US20080213996A1 Designs and methods for conductive bumps 有权
标题翻译：导电凸块的设计和方法
公开(公告)号：US20080213996A1
公开(公告)日：2008-09-04
申请号：US11894627
申请日：2007-08-20
申请人： Valery M. Dubin , Sridhar Balakrishnan , Mark Bohr
发明人： Valery M. Dubin , Sridhar Balakrishnan , Mark Bohr
IPC分类号： H01L21/44
CPC分类号： H01L24/13 , H01L21/288 , H01L21/4853 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05124 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/11614 , H01L2224/13026 , H01L2224/13084 , H01L2224/13099 , H01L2224/13111 , H01L2224/13113 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2224/13166 , H01L2224/13564 , H01L2224/13611 , H01L2224/13639 , H01L2224/13647 , H01L2224/29111 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01051 , H01L2924/01057 , H01L2924/01058 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/3011 , H01L2924/351 , H01L2924/35121 , H01L2924/3651 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
摘要翻译：与模具包装相关的方法，技术和结构。在一个示例性实施例中，管芯封装互连结构包括半导体衬底和与半导体衬底接触的第一导电层。第一导电层可以包括基底层金属。基底层金属可以包括Cu。示例性实施方式还可以包括与第一导电层接触的扩散阻挡层和在扩散阻挡层顶部的润湿层。凸起层可以驻留在润湿层的顶部，其中凸起层可以包括Sn，并且Sn可以被电镀。扩散阻挡层可以是无电解的并且可以适于防止Cu和Sn扩散通过扩散阻挡层。此外，扩散阻挡层可以进一步适于抑制凸块层中的晶须型形成。

8. 发明申请

US20080003366A1 Method of forming a conducting layer on a conducting and non-conducting substrate 审中-公开
标题翻译：在导电和非导电基底上形成导电层的方法
公开(公告)号：US20080003366A1
公开(公告)日：2008-01-03
申请号：US11479535
申请日：2006-06-30
申请人： Valery M. Dubin , Ramanan V. Chebiam , Michael Goldstein , Toru Imori
发明人： Valery M. Dubin , Ramanan V. Chebiam , Michael Goldstein , Toru Imori
IPC分类号： B05D1/40
CPC分类号： C23C18/1841 , C23C18/1653 , C23C18/1827 , C23C18/38 , H01L21/288 , H01L21/76873
摘要： A method of processing a substrate is described. A coupling agent and a metal ion solution are applied to the substrate. An activating solution is applied to activate metal ions of the metal ion solution to create a metal film out of the ions. Atoms of the metal film are used to catalyze a metal of a base metal solution to form a metal layer. The metal layer can be used as a seed layer for electroplating purposes.
摘要翻译：描述了一种处理衬底的方法。将偶联剂和金属离子溶液施加到基材上。施加激活溶液以激活金属离子溶液的金属离子，以产生离子之外的金属膜。金属膜的原子用于催化贱金属溶液的金属以形成金属层。金属层可以用作用于电镀目的的种子层。

9. 发明授权

US07304388B2 Method and apparatus for an improved air gap interconnect structure 有权
标题翻译：用于改进气隙互连结构的方法和装置
公开(公告)号：US07304388B2
公开(公告)日：2007-12-04
申请号：US10608948
申请日：2003-06-26
申请人： Valery M. Dubin , Peter K. Moon
发明人： Valery M. Dubin , Peter K. Moon
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/7682 , H01L21/76849 , H01L21/7685 , H01L21/76879 , H01L23/5222 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.
摘要翻译：在一个实施例中，一种装置包括具有在层间电介质（ILD）中形成的至少一个互连的第一层，在第一层上形成的具有第二至少一个互连的第二层，在第二层上形成的第三层，第三层限定第二至少一个互连和第三层之间的至少一个空气间隙，以及至少一个分流器，其选择性地覆盖第一和第二至少一个互连。在另一个实施例中，一种方法包括形成包括ILD和第一至少一个互连的第一层，在第一层上形成第二层，第二层具有第二至少一个互连，在第一层上沉积至少一个分流以及第二至少一个互连，在所述第二层上形成第三层，以及蒸发所述第二层的一部分以在所述第二至少一个互连和所述第三层之间产生至少一个空气间隙。

10. 发明授权

US07223694B2 Method for improving selectivity of electroless metal deposition 有权
标题翻译：提高无电金属沉积选择性的方法
公开(公告)号：US07223694B2
公开(公告)日：2007-05-29
申请号：US10459131
申请日：2003-06-10
申请人： Chin-Chang Cheng , Valery M. Dubin , Peter K. Moon
发明人： Chin-Chang Cheng , Valery M. Dubin , Peter K. Moon
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/288
摘要： A method of depositing a metal cladding on conductors in a damascene process is described. The potential between, for instance, cobalt ions in electroless solution and the surface of an ILD between the conductors is adjusted so as to repel the metal from the ILD.
摘要翻译：描述了在镶嵌工艺中在导体上沉积金属包层的方法。调整例如化学溶液中的钴离子与导体之间的ILD表面之间的电位，以便从ILD排斥金属。

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