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1. 发明申请

US20120080769A1 ESD DEVICE AND METHOD 审中-公开
标题翻译： ESD器件和方法
公开(公告)号：US20120080769A1
公开(公告)日：2012-04-05
申请号：US12896390
申请日：2010-10-01
申请人： Umesh Sharma , Harry Yue Gee , Der Min Liou , David D. Marreiro , Sudhama C. Shastri
发明人： Umesh Sharma , Harry Yue Gee , Der Min Liou , David D. Marreiro , Sudhama C. Shastri
IPC分类号： H01L27/07 , H01L21/335 , H01L21/336 , H01L29/41 , H01L21/283
CPC分类号： H01L29/66106 , H01L24/05 , H01L27/0255 , H01L29/8611 , H01L29/866 , H01L2224/04042 , H01L2224/05552 , H01L2224/05556 , H01L2224/0603 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48472 , H01L2924/12035 , H01L2924/1305 , H01L2924/13091 , H01L2924/15747 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.
摘要翻译：一种半导体部件和半导体部件的制造方法，其中，所述半导体部件包括具有至少两个二极管和齐纳二极管的瞬态电压抑制结构。根据实施例，提供了包括外延层的半导体材料。在外延层的表面上形成至少两个二极管和齐纳二极管，其中至少两个二极管可以与齐纳二极管相邻。

2. 发明申请

US20120080803A1 METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE 有权
标题翻译：制造半导体元件和结构的方法
公开(公告)号：US20120080803A1
公开(公告)日：2012-04-05
申请号：US12896416
申请日：2010-10-01
申请人： Phillip Holland , Rong Liu , Umesh Sharma , Der Min Liou , David D. Marreiro , Sudhama C. Shastri
发明人： Phillip Holland , Rong Liu , Umesh Sharma , Der Min Liou , David D. Marreiro , Sudhama C. Shastri
IPC分类号： H01L23/52
CPC分类号： H01L28/10 , H01L23/5227 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component and methods for manufacturing the semiconductor component that includes a three dimensional helically shaped common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke.
摘要翻译：一种半导体元件及其制造方法，该半导体元件包括三维螺旋状共模扼流圈。根据实施例，瞬态电压抑制装置可以耦合到单片集成的共模扼流圈。

3. 发明授权

US08766401B2 Method of manufacturing a semiconductor component and structure 有权
标题翻译：制造半导体元件和结构的方法
公开(公告)号：US08766401B2
公开(公告)日：2014-07-01
申请号：US12896416
申请日：2010-10-01
申请人： Phillip Holland , Rong Liu , Umesh Sharma , Der Min Liou , David D. Marreiro , Sudhama C. Shastri
发明人： Phillip Holland , Rong Liu , Umesh Sharma , Der Min Liou , David D. Marreiro , Sudhama C. Shastri
IPC分类号： H01L29/00 , H01L23/48
CPC分类号： H01L28/10 , H01L23/5227 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component and methods for manufacturing the semiconductor component that includes a three dimensional helically shaped common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke.
摘要翻译：一种半导体元件及其制造方法，该半导体元件包括三维螺旋状共模扼流圈。根据实施例，瞬态电压抑制装置可以耦合到单片集成的共模扼流圈。

4. 发明申请

US20080258263A1 High Current Steering ESD Protection Zener Diode And Method 审中-公开
标题翻译：大电流转向ESD保护齐纳二极管和方法
公开(公告)号：US20080258263A1
公开(公告)日：2008-10-23
申请号：US11738176
申请日：2007-04-20
申请人： Harry Yue Gee , Adam J. Whitworth , Umesh Sharma
发明人： Harry Yue Gee , Adam J. Whitworth , Umesh Sharma
IPC分类号： H01L29/866 , G05F1/00 , H01L21/20
CPC分类号： H01L29/866 , H01L27/0255 , H01L29/66106
摘要： A method of fabricating a N+/P+ zener diode where the reverse breakdown occurs in a controlled, and uniform manner leading to improved speed of operation and increase in current handling capability.
摘要翻译：一种制造N + / P +齐纳二极管的方法，其中反向击穿以受控和均匀的方式发生，导致改进的操作速度和电流处理能力的增加。

5. 发明授权

US07972521B2 Method of making reliable wafer level chip scale package semiconductor devices 有权
标题翻译：制造可靠的晶圆级芯片级封装半导体器件的方法
公开(公告)号：US07972521B2
公开(公告)日：2011-07-05
申请号：US11685085
申请日：2007-03-12
申请人： Umesh Sharma , Harry Yue Gee , Phillip Gene Holland
发明人： Umesh Sharma , Harry Yue Gee , Phillip Gene Holland
IPC分类号： H05K3/00
CPC分类号： H01L24/10 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/00014 , H01L2924/01005 , H01L2924/01019 , H01L2924/01033 , H01L2924/01057 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , Y10T29/4913 , H01L2924/00 , H01L2224/05099
摘要： The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using an insulating material applied in a highly compressive manner is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer.
摘要翻译：本发明涉及一种制造坚固的晶片级芯片级封装的方法，特别涉及一种防止在焊料流动期间和之后的多个热回流步骤中的钝化层破裂的方法。在一个实施例中，使用使用以高度压缩方式施加的绝缘材料形成的钝化层。在另一方面，将另一层施加在钝化层上以有助于防止钝化层的破裂。

6. 发明申请

US20080227240A1 Method of Making Reliable Wafer Level Chip Scale Package Semiconductor Devices 有权
标题翻译：制造可靠的晶片级芯片级封装半导体器件的方法
公开(公告)号：US20080227240A1
公开(公告)日：2008-09-18
申请号：US11685085
申请日：2007-03-12
申请人： Umesh Sharma , Harry Yue Gee , Phillip Gene Holland
发明人： Umesh Sharma , Harry Yue Gee , Phillip Gene Holland
IPC分类号： H01L21/78
CPC分类号： H01L24/10 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/00014 , H01L2924/01005 , H01L2924/01019 , H01L2924/01033 , H01L2924/01057 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , Y10T29/4913 , H01L2924/00 , H01L2224/05099
摘要： The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using a highly compressive insulating material is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer.
摘要翻译：本发明涉及一种制造坚固的晶片级芯片级封装的方法，特别涉及一种防止在焊料流动期间和之后的多个热回流步骤中的钝化层破裂的方法。在一个实施例中，使用使用高度压缩的绝缘材料形成的钝化层。在另一方面，将另一层施加在钝化层上以有助于防止钝化层的破裂。

7. 发明授权

US07576370B2 Low operating voltage electro-static discharge device and method 有权
标题翻译：低工作电压静电放电装置及方法
公开(公告)号：US07576370B2
公开(公告)日：2009-08-18
申请号：US11738152
申请日：2007-04-20
申请人： Harry Yue Gee , Umesh Sharma
发明人： Harry Yue Gee , Umesh Sharma
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L27/0255 , H01L27/0259 , H01L29/8618
摘要： The present invention describes ESD apparatus, methods of forming the same, and methods of providing ESD protection. In certain aspects, the invention achieves the desired turn-on voltage and maintains low leakage in the ESD apparatus, and the methods of providing ESD protection. In one aspect, a zener diode that has a positive trigger voltage is used to quickly turn-on a transistor. In another aspect, different zener diodes that have positive and negative trigger voltages, respectively, are used to quickly turn on a transistor. In still another aspect, a linearly graded P-region is used to implement the ESD device of the present invention.
摘要翻译：本发明描述了ESD装置，其形成方法以及提供ESD保护的方法。在某些方面，本发明实现了所需的导通电压，并且在ESD装置中保持低泄漏，以及提供ESD保护的方法。在一个方面，具有正触发电压的齐纳二极管用于快速导通晶体管。在另一方面，分别具有正和负触发电压的不同齐纳二极管用于快速导通晶体管。在另一方面，使用线性渐变P区来实现本发明的ESD装置。

8. 发明申请

US20080259518A1 Low Operating Voltage Electro-Static Discharge Device And Method 有权
标题翻译：低工作电压静电放电装置及方法
公开(公告)号：US20080259518A1
公开(公告)日：2008-10-23
申请号：US11738152
申请日：2007-04-20
申请人： Harry Yue Gee , Umesh Sharma
发明人： Harry Yue Gee , Umesh Sharma
IPC分类号： H05F3/00
CPC分类号： H01L27/0255 , H01L27/0259 , H01L29/8618
摘要： The present invention describes ESD apparatus, methods of forming the same, and methods of providing ESD protection. In certain aspects, the invention achieves the desired turn-on voltage and maintains low leakage in the ESD apparatus, and the methods of providing ESD protection. In one aspect, a zener diode that has a positive trigger voltage is used to quickly turn-on a transistor. In another aspect, different zener diodes that have positive and negative trigger voltages, respectively, are used to quickly turn on a transistor. In still another aspect, a linearly graded P-region is used to implement the ESD device of the present invention.
摘要翻译：本发明描述了ESD装置，其形成方法以及提供ESD保护的方法。在某些方面，本发明实现了所需的导通电压，并且在ESD装置中保持低泄漏，以及提供ESD保护的方法。在一个方面，具有正触发电压的齐纳二极管用于快速导通晶体管。在另一方面，分别具有正和负触发电压的不同齐纳二极管用于快速导通晶体管。在另一方面，使用线性渐变P区来实现本发明的ESD装置。

9. 发明授权

US5621233A Electrically programmable read-only memory cell 失效
标题翻译：电可编程只读存储单元
公开(公告)号：US5621233A
公开(公告)日：1997-04-15
申请号：US462410
申请日：1995-06-05
申请人： Umesh Sharma , Michael P. Woo
发明人： Umesh Sharma , Michael P. Woo
IPC分类号： H01L21/8247 , H01L29/788 , H01L29/76
CPC分类号： H01L27/11521
摘要： EPROM cells include T-shaped floating gates (61, 171) and control gates that surround virtually all of the floating gates (61, 171) except for the portion of the floating gates (61, 171) that lie on a gate dielectric layer (51, 151). The EPROM cells may include customized well regions (22, 122) to allow flash erasing or individual cell erasing for electrically erasable EPROMs. Many different configurations of the memory cells are possible. The configurations of the source regions, drain regions, and well regions (22, 122) may be determined by how a user of the memory cells wants to program or erase the memory cells.
摘要翻译： EPROM单元包括除了浮置栅极（61,171）的位于栅介质层上的部分以外的实际上围绕所有浮动栅极（61,171）的T形浮动栅极（61,171）和控制栅极（ 51，151）。 EPROM单元可以包括定制的阱区域（22,122），以允许电擦除EPROM的闪存擦除或单独的单元擦除。存储单元的许多不同配置是可能的。源极区域，漏极区域和阱区域（22,122）的配置可以由存储器单元的用户想如何编程或擦除存储器单元来确定。

10. 发明授权

US5498560A Process for forming an electrically programmable read-only memory cell 失效
标题翻译：用于形成电可编程只读存储器单元的工艺
公开(公告)号：US5498560A
公开(公告)日：1996-03-12
申请号：US311162
申请日：1994-09-16
申请人： Umesh Sharma , Michael P. Woo
发明人： Umesh Sharma , Michael P. Woo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： EPROM cells include T-shaped floating gates (61, 171) and control gates that surround virtually all of the floating gates (61, 171) except for the portion of the floating gates (61, 171) that lie on a gate dielectric layer (51, 151). The EPROM cells may include customized well regions (22, 122) to allow flash erasing or individual cell erasing for electrically erasable EPROMs. Many different configurations of the memory cells are possible. The configurations of the source regions, drain regions, and well regions (22, 122) may be determined by how a user of the memory cells wants to program or erase the memory cells.
摘要翻译： EPROM单元包括除了浮置栅极（61,171）的位于栅介质层上的部分以外的实际上围绕所有浮动栅极（61,171）的T形浮动栅极（61,171）和控制栅极（ 51，151）。 EPROM单元可以包括定制的阱区域（22,122），以允许电擦除EPROM的闪存擦除或单独的单元擦除。存储单元的许多不同配置是可能的。源极区域，漏极区域和阱区域（22,122）的配置可以由存储器单元的用户想如何编程或擦除存储器单元来确定。

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