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1. 发明申请

US20060214231A1 Nonplanar device with thinned lower body portion and method of fabrication 有权
公开(公告)号：US20060214231A1
公开(公告)日：2006-09-28
申请号：US11440313
申请日：2006-05-23
申请人： Uday Shah , Brian Doyle , Justin Brask , Robert Chau , Thomas Letson
发明人： Uday Shah , Brian Doyle , Justin Brask , Robert Chau , Thomas Letson
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/42384 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/7856 , H01L2924/13067 , Y10S438/978
摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

2. 发明申请

US20060086977A1 Nonplanar device with thinned lower body portion and method of fabrication 审中-公开
公开(公告)号：US20060086977A1
公开(公告)日：2006-04-27
申请号：US10973228
申请日：2004-10-25
申请人： Uday Shah , Brian Doyle , Justin Brask , Robert Chau , Thomas Letson
发明人： Uday Shah , Brian Doyle , Justin Brask , Robert Chau , Thomas Letson
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/42384 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/7856 , H01L2924/13067 , Y10S438/978
摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

3. 发明申请

US20060071275A1 Nonplanar transistors with metal gate electrodes 有权
公开(公告)号：US20060071275A1
公开(公告)日：2006-04-06
申请号：US10956279
申请日：2004-09-30
申请人： Justin Brask , Brian Doyle , Jack Kavalieros , Mark Doczy , Uday Shah , Robert Chau
发明人： Justin Brask , Brian Doyle , Jack Kavalieros , Mark Doczy , Uday Shah , Robert Chau
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/41791 , H01L29/66439 , H01L29/66545 , H01L29/66795 , Y10S438/926 , Y10S438/974
摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

4. 发明申请

US20060051957A1 Method for making a semiconductor device that includes a metal gate electrode 有权
标题翻译：制造包括金属栅电极的半导体器件的方法
公开(公告)号：US20060051957A1
公开(公告)日：2006-03-09
申请号：US10936114
申请日：2004-09-07
申请人： Justin Brask , Jack Kavalieros , Mark Doczy , Matthew Metz , Suman Datta , Uday Shah , Brian Doyle , Robert Chau
发明人： Justin Brask , Jack Kavalieros , Mark Doczy , Matthew Metz , Suman Datta , Uday Shah , Brian Doyle , Robert Chau
IPC分类号： H01L21/4763
CPC分类号： H01L21/82385 , H01L21/28114 , H01L21/30608 , H01L21/823828 , H01L29/42376 , H01L29/66545 , Y10S438/926
摘要： A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. After the sacrificial structure is removed to generate a trench, a metal gate electrode is formed within the trench.
摘要翻译：描述制造半导体器件的方法。该方法包括在衬底上形成介电层和包括第一层和第二层的牺牲结构，使得第二层形成在第一层上并且比第一层更宽。在除去牺牲结构以产生沟槽之后，在沟槽内形成金属栅电极。

5. 发明申请

US20050266692A1 Method of patterning a film 有权
标题翻译：图案化方法
公开(公告)号：US20050266692A1
公开(公告)日：2005-12-01
申请号：US10859328
申请日：2004-06-01
申请人： Justin Brask , Brian Doyle , Uday Shah , Robert Chau
发明人： Justin Brask , Brian Doyle , Uday Shah , Robert Chau
IPC分类号： H01L21/302 , H01L21/308 , H01L21/311 , H01L21/461 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/31111 , H01L21/3081 , H01L21/76838 , H01L29/785
摘要： A method of patterning a thin film. The method includes forming a mask on a film to be patterned. The film is then etched in alignment with the mask to form a patterned film having a pair of laterally opposite sidewalls. A protective layer is formed on the pair of laterally opposite sidewalls. Next, the mask is removed from above the patterned film. After removing the mask from the patterned film, the protective layer is removed from the sidewalls.
摘要翻译：图案化薄膜的方法。该方法包括在待图案化的膜上形成掩模。然后将膜与掩模对准地蚀刻以形成具有一对横向相对的侧壁的图案化膜。在一对横向相对的侧壁上形成保护层。接下来，从图案化膜的上方去除掩模。在从图案化的膜去除掩模之后，从侧壁去除保护层。

6. 发明申请

US20070069293A1 Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby 有权
标题翻译：用于将体积衬底上的平面和非平面CMOS晶体管和由此制成的制品集成的工艺
公开(公告)号：US20070069293A1
公开(公告)日：2007-03-29
申请号：US11238444
申请日：2005-09-28
申请人： Jack Kavalieros , Justin Brask , Brian Doyle , Uday Shah , Suman Datta , Mark Doczy , Matthew Metz , Robert Chau
发明人： Jack Kavalieros , Justin Brask , Brian Doyle , Uday Shah , Suman Datta , Mark Doczy , Matthew Metz , Robert Chau
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L21/823828 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/1037 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
摘要翻译：一种能够将平面和非平面晶体管集成到体半导体衬底上的工艺，其中所有晶体管的沟道可以在连续的宽度范围内定义。

7. 发明申请

US20070001173A1 Semiconductor device structures and methods of forming semiconductor structures 有权
标题翻译：半导体器件结构和形成半导体结构的方法
公开(公告)号：US20070001173A1
公开(公告)日：2007-01-04
申请号：US11158661
申请日：2005-06-21
申请人： Justin Brask , Jack Kavalieros , Uday Shah , Suman Datta , Amlan Majumdar , Robert Chau , Brian Doyle
发明人： Justin Brask , Jack Kavalieros , Uday Shah , Suman Datta , Amlan Majumdar , Robert Chau , Brian Doyle
IPC分类号： H01L29/10
CPC分类号： H01L29/7853 , H01L21/30608 , H01L21/30617 , H01L21/3085 , H01L21/84 , H01L29/04 , H01L29/045 , H01L29/0657 , H01L29/51 , H01L29/66795 , H01L29/78681 , H01L29/78684
摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
摘要翻译：对半导体膜的图案化方法进行说明。根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密并且其中所述硬掩模形成在所述第二晶体平面上。接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

8. 发明授权

US07071064B2 U-gate transistors and methods of fabrication 失效
标题翻译： U型栅极晶体管及其制造方法
公开(公告)号：US07071064B2
公开(公告)日：2006-07-04
申请号：US10949994
申请日：2004-09-23
申请人： Brian Doyle , Surinder Singh , Uday Shah , Justin Brask , Robert Chau
发明人： Brian Doyle , Surinder Singh , Uday Shah , Justin Brask , Robert Chau
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/7853 , H01L29/66795
摘要： A process is described for manufacturing of non-planar multi-corner transistor structures. A fin of a semiconductor material having a mask on a top surface of the fin is formed on a first insulating layer. A second insulating layer is formed on the fin exposing a top surface of the mask, wherein a protection layer is deposited between the fin and the second insulating layer. Next, the mask is removed and spacers are formed on the fin adjacent to the protection layer. A recess having a bottom and opposing sidewalls is formed in the fin. A gate dielectric layer and a gate electrode are formed on the top surface, the opposing sidewalls of the fin and on the bottom and on the opposing sidewalls of the recess in the fin. A source region and a drain region are formed in the fin at the opposite sides of the gate electrode.
摘要翻译：描述了用于制造非平面多角晶体管结构的工艺。在第一绝缘层上形成具有在鳍的顶表面上的掩模的半导体材料的鳍。在翅片上形成第二绝缘层，露出掩模的顶表面，其中保护层沉积在散热片和第二绝缘层之间。接下来，去除掩模，并且在与保护层相邻的翅片上形成间隔物。在翅片中形成具有底部和相对侧壁的凹部。栅极电介质层和栅电极形成在翅片的顶表面，翅片的相对侧壁和底部上以及凹槽的相对侧壁上。源极区域和漏极区域形成在栅极的相对侧的鳍片中。

9. 发明申请

US20060138553A1 Nonplanar transistors with metal gate electrodes 有权
公开(公告)号：US20060138553A1
公开(公告)日：2006-06-29
申请号：US11362453
申请日：2006-02-24
申请人： Justin Brask , Brian Doyle , Jack Kavalleros , Mark Doczy , Uday Shah , Robert Chau
发明人： Justin Brask , Brian Doyle , Jack Kavalleros , Mark Doczy , Uday Shah , Robert Chau
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/41791 , H01L29/66439 , H01L29/66545 , H01L29/66795 , Y10S438/926 , Y10S438/974
摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

10. 发明申请

US20070231997A1 Stacked multi-gate transistor design and method of fabrication 有权
标题翻译：堆叠多栅晶体管的设计与制作方法
公开(公告)号：US20070231997A1
公开(公告)日：2007-10-04
申请号：US11395860
申请日：2006-03-31
申请人： Brian Doyle , Titash Rakshit , Robert Chau , Suman Datta , Justin Brask , Uday Shah
发明人： Brian Doyle , Titash Rakshit , Robert Chau , Suman Datta , Justin Brask , Uday Shah
IPC分类号： H01L21/8242
CPC分类号： H01L29/7853 , H01L29/66818
摘要： A multi-body thickness (MBT) field effect transistor (FET) comprises a silicon body formed on a substrate. The silicon body may comprise a wide section and a narrow section between the wide section and the substrate. The silicon body may comprise more than one pair of a wide section and a narrow section, each pair being located at a different height of the silicon body. The silicon body is surrounded by a gate material on three sides. The substrate may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The MBT-FET combines the advantages of a wide fin device and a narrow fin device.
摘要翻译：多体厚度（MBT）场效应晶体管（FET）包括形成在衬底上的硅体。硅体可以包括在宽部分和基底之间的宽的部分和窄的部分。硅体可以包括多于一对宽的部分和窄的部分，每对位于硅体的不同高度处。硅体由三面的栅极材料包围。衬底可以是体硅衬底或绝缘体上硅（SOI）衬底。 MBT-FET结合了宽鳍片器件和窄鳍片器件的优点。

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