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1. 发明公开

US20240371699A1 Semiconductor structure and manufacturing method thereof 审中-公开
公开(公告)号：US20240371699A1
公开(公告)日：2024-11-07
申请号：US18208896
申请日：2023-06-13
申请人： UNITED MICROELECTRONICS CORP.
发明人： Ching-Ling Lin , Wen-An Liang , Chia-Fu Hsu , Huang-Ren Wei
IPC分类号： H01L21/8234 , H01L21/768 , H01L23/528 , H01L27/088 , H01L29/66
CPC分类号： H01L21/82345 , H01L21/76834 , H01L21/76877 , H01L21/823468 , H01L21/823475 , H01L23/528 , H01L27/088 , H01L29/6656
摘要： The invention provides a semiconductor structure, the semiconductor structure comprises a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, a plurality of first metal layers located on a part of the gate structures, and the first metal layers are respectively electrically connected with the corresponding gate structures, at least one second metal layer, the second metal layer is bridged over at least two of the gate structures, wherein the depth of the first metal layer is greater than that of the second metal layer.

2. 发明申请

US20190019731A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20190019731A1
公开(公告)日：2019-01-17
申请号：US15647031
申请日：2017-07-11
申请人： United Microelectronics Corp.
发明人： Ching-Ling Lin , Wen-An Liang , Chen-Ming Huang
IPC分类号： H01L21/8234 , H01L21/033
摘要： A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.

3. 发明授权

US09748144B1 Method of fabricating semiconductor device 有权
公开(公告)号：US09748144B1
公开(公告)日：2017-08-29
申请号：US15138228
申请日：2016-04-26
申请人： UNITED MICROELECTRONICS CORP.
发明人： Ching-Ling Lin , Yi-Wen Chen , Chen-Ming Huang , Ren-Peng Huang , Ching-Fu Lin
IPC分类号： H01L21/00 , H01L21/8234 , H01L29/66 , H01L21/3105 , H01L21/3213 , H01L29/423 , H01L21/321 , H01L21/033 , H01L29/51 , H01L21/28 , H01L27/11
CPC分类号： H01L21/823456 , H01L21/0332 , H01L21/28079 , H01L21/28088 , H01L21/31055 , H01L21/32115 , H01L21/32139 , H01L21/823431 , H01L21/823437 , H01L27/1104 , H01L27/1116 , H01L28/00 , H01L29/42376 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.

4. 发明申请

US20140302677A1 METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURES 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US20140302677A1
公开(公告)日：2014-10-09
申请号：US13859720
申请日：2013-04-09
申请人： UNITED MICROELECTRONICS CORP.
发明人： Ching-Ling Lin , Po-Chao Tsao , Chia-Jui Liang , Chien-Ting Lin
IPC分类号： H01L21/311 , H01L21/3105
CPC分类号： H01L21/3086 , H01L21/823468 , H01L21/823864 , H01L29/66795
摘要： A method for manufacturing semiconductor structures includes providing a substrate having a plurality of mandrel patterns and a plurality of dummy patterns, simultaneously forming a plurality of first spacers on sidewalls of the mandrel patterns and a plurality of second spacers on sidewalls of the dummy patterns, and removing the second spacers and the mandrel patterns to form a plurality of spacer patterns on the substrate.
摘要翻译：一种用于制造半导体结构的方法，包括提供具有多个心轴图案和多个虚拟图案的基板，同时在心轴图案的侧壁上形成多个第一间隔件，在虚设图案的侧壁上形成多个第二间隔件，以及移除第二间隔件和心轴图案以在基底上形成多个间隔图案。

5. 发明申请

US20140295650A1 METHOD FOR FABRICATING PATTERNED STRUCTURE OF SEMICONDUCTOR DEVICE 有权
标题翻译：用于制作半导体器件的图案结构的方法
公开(公告)号：US20140295650A1
公开(公告)日：2014-10-02
申请号：US13851113
申请日：2013-03-27
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chia-Jung Li , Chia-Jui Liang , Po-Chao Tsao , Ching-Ling Lin , En-Chiuan Liou
IPC分类号： H01L21/308 , H01L21/311 , H01L21/02
CPC分类号： H01L21/308 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L21/76229
摘要： A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.
摘要翻译：提供一种制造半导体器件的图案化结构的方法。首先，提供具有第一区域和第二区域的基板。然后在基板上顺序地形成目标层，硬掩模层和第一图案化掩模层。通过使用第一图案化掩模层作为蚀刻掩模来执行第一蚀刻工艺，从而形成图案化的硬掩模层。间隔物分别形成在图案化的硬掩模层的每个侧壁上。然后，在基板上形成第二图案化掩模层。执行第二蚀刻工艺以蚀刻第二区域中的图案化硬掩模层。在间隔物曝光之后，将图案化的硬掩模层用作蚀刻掩模，并且去除曝光的目标层，直到相应的基板的曝光。

6. 发明申请

US20200328126A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20200328126A1
公开(公告)日：2020-10-15
申请号：US16914483
申请日：2020-06-29
申请人： UNITED MICROELECTRONICS CORP.
发明人： Fu-Jung Chuang , Ching-Ling Lin , Po-Jen Chuang , Yu-Ren Wang , Wen-An Liang , Chia-Ming Kuo , Guan-Wei Huang , Yuan-Yu Chung , I-Ming Tseng
IPC分类号： H01L21/8238 , H01L27/092 , H01L21/762
摘要： A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.

7. 发明授权

US10679903B2 Semiconductor device and method for fabricating the same 有权
公开(公告)号：US10679903B2
公开(公告)日：2020-06-09
申请号：US15859775
申请日：2018-01-02
申请人： UNITED MICROELECTRONICS CORP.
发明人： Ching-Ling Lin , Wen-An Liang , Chen-Ming Huang
IPC分类号： H01L21/8234 , H01L21/764 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/78
摘要： A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.

8. 发明申请

US20200035568A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20200035568A1
公开(公告)日：2020-01-30
申请号：US16589032
申请日：2019-09-30
申请人： UNITED MICROELECTRONICS CORP.
发明人： Fu-Jung Chuang , Ching-Ling Lin , Po-Jen Chuang , Yu-Ren Wang , Wen-An Liang , Chia-Ming Kuo , Guan-Wei Huang , Yuan-Yu Chung , I-Ming Tseng
IPC分类号： H01L21/8238 , H01L21/762 , H01L27/092
摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.

9. 发明申请

US20190172753A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20190172753A1
公开(公告)日：2019-06-06
申请号：US15859775
申请日：2018-01-02
申请人： UNITED MICROELECTRONICS CORP.
发明人： Ching-Ling Lin , Wen-An Liang , Chen-Ming Huang
IPC分类号： H01L21/8234 , H01L21/764 , H01L27/088 , H01L29/06
摘要： A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.

10. 发明授权

US09312356B1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09312356B1
公开(公告)日：2016-04-12
申请号：US14613379
申请日：2015-02-04
申请人： UNITED MICROELECTRONICS CORP.
发明人： Ching-Ling Lin , Chih-Sen Huang , Yi-Wen Chen
IPC分类号： H01L21/70 , H01L29/49 , H01L21/02 , H01L21/768 , H01L21/311 , H01L21/28
CPC分类号： H01L29/4966 , H01L21/28518 , H01L21/76834 , H01L21/76897 , H01L29/41783 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66628
摘要： The semiconductor device includes a gate electrode, a first interlayer dielectric, a first mask layer, a second mask layer and a second interlayer dielectric. The first interlayer dielectric surrounds the periphery of the gate electrode, and the first mask layer is disposed on the gate electrode. The first mask layer and the gate electrode have at least one same metal component. The second mask layer is disposed on the sidewalls of the first mask layer, and the second interlayer dielectric is disposed on the second mask layer and in direct contact with the first interlayer dielectric.
摘要翻译：半导体器件包括栅电极，第一层间电介质，第一掩模层，第二掩模层和第二层间电介质。第一层间电介质围绕栅电极的周边，并且第一掩模层设置在栅电极上。第一掩模层和栅电极具有至少一个相同的金属成分。第二掩模层设置在第一掩模层的侧壁上，第二层间电介质设置在第二掩模层上并与第一层间电介质直接接触。

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