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1. 发明申请

US20210193575A1 MANUFACTURING METHOD OF CONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20210193575A1
公开(公告)日：2021-06-24
申请号：US17191730
申请日：2021-03-04
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chen-Yi Weng , Shih-Che Huang , Ching-Li Yang , Chih-Sheng Chang
IPC分类号： H01L23/528 , H01L23/532 , H01L23/498 , H01L23/522
摘要： A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.

2. 发明授权

US10892235B2 Die seal ring and manufacturing method thereof 有权
公开(公告)号：US10892235B2
公开(公告)日：2021-01-12
申请号：US16135997
申请日：2018-09-19
申请人： United Microelectronics Corp.
发明人： Shih-Che Huang , Shih-Hsien Chen , Ching-Li Yang , Chih-Sheng Chang
IPC分类号： H01L21/764 , H01L21/768 , H01L23/58 , H01L23/10 , H01L23/522 , H01L21/48 , H01L23/00
摘要： A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.

3. 发明申请

US20140291801A1 ANTI-FUSE STRUCTURE AND PROGRAMMING METHOD THEREOF 有权
标题翻译：防冻结构及其编程方法
公开(公告)号：US20140291801A1
公开(公告)日：2014-10-02
申请号：US13854142
申请日：2013-04-01
申请人： United Microelectronics CORP.
发明人： Chu-Fu Lin , Chien-Li Kuo , Ching-Li Yang
IPC分类号： H01L23/525 , H01L23/00
CPC分类号： H01L23/5252 , H01L23/525 , H01L23/5254 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05147 , H01L2224/05166 , H01L2224/05184 , H01L2224/05572 , H01L2224/13147 , H01L2224/13166 , H01L2224/13184 , H01L2924/12042 , H01L2924/13091 , H01L2924/00 , H01L2924/00014
摘要： A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically.
摘要翻译：反熔丝编程方法包括以下步骤。首先，提供绝缘层。在绝缘层上限定反熔丝区域。反熔丝嵌入在绝缘层的反熔丝区域内。反熔丝包括至少第一导体和第二导体。然后，通过激光去除绝缘层的一部分，以在绝缘层中形成抗熔丝开口。第一导体的一部分和第二导体的一部分通过反熔丝开口露出。之后，在反熔丝开口中形成凸起下的金属层，以电连接第一导体和第二导体。

4. 发明申请

US20130299949A1 Through Silicon Via and Method of Forming the Same 有权
标题翻译：通过硅通孔及其形成方法
公开(公告)号：US20130299949A1
公开(公告)日：2013-11-14
申请号：US13947125
申请日：2013-07-22
申请人： UNITED MICROELECTRONICS CORP.
发明人： Kuo-Hsiung Huang , Chun-Mao Chiou , Hsin-Yu Chen , Yu-Han Tsai , Ching-Li Yang , Home-Been Cheng
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76843 , H01L21/76898 , H01L23/481 , H01L23/525 , H01L2224/13 , H01L2924/1461 , H01L2924/00
摘要： The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface.
摘要翻译：本发明涉及一种硅通孔（TSV）。 TSV设置在包括穿过基板的第一表面和第二表面的通孔的基板中。 TSV包括绝缘层，阻挡层，缓冲层和导电电极。绝缘层设置在通孔开口的表面上。阻挡层设置在绝缘层的表面上。缓冲层设置在阻挡层的表面上。导电电极设置在缓冲层的表面上，通孔开口的其余部分被导电电极完全填充。缓冲层的一部分还在第二表面的一侧覆盖导电电极的表面，并且所述部分与第二表面平齐。

5. 发明授权

US09312208B2 Through silicon via structure 有权
公开(公告)号：US09312208B2
公开(公告)日：2016-04-12
申请号：US14521456
申请日：2014-10-22
申请人： UNITED MICROELECTRONICS CORP.
发明人： Hsin-Yu Chen , Home-Been Cheng , Yu-Han Tsai , Ching-Li Yang
IPC分类号： H01L21/44 , H01L23/48 , H01L21/768 , H01L23/522
CPC分类号： H01L23/481 , H01L21/7684 , H01L21/76898 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via.

6. 发明授权

US10978391B2 Connection structure of semiconductor device and manufacturing method thereof 有权
公开(公告)号：US10978391B2
公开(公告)日：2021-04-13
申请号：US15730744
申请日：2017-10-12
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chen-Yi Weng , Shih-Che Huang , Ching-Li Yang , Chih-Sheng Chang
IPC分类号： H01L23/528 , H01L23/522 , H01L23/532 , H01L23/498
摘要： A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.

7. 发明申请

US20200066657A1 DIE SEAL RING AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20200066657A1
公开(公告)日：2020-02-27
申请号：US16135997
申请日：2018-09-19
申请人： United Microelectronics Corp.
发明人： Shih-Che Huang , Shih-Hsien Chen , Ching-Li Yang , Chih-Sheng Chang
IPC分类号： H01L23/58 , H01L23/10 , H01L23/00 , H01L21/48 , H01L23/522
摘要： A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.

8. 发明授权

US09048246B2 Die seal ring and method of forming the same 有权
标题翻译：模具密封环及其形成方法
公开(公告)号：US09048246B2
公开(公告)日：2015-06-02
申请号：US13921174
申请日：2013-06-18
申请人： UNITED MICROELECTRONICS CORP.
发明人： Ming-Te Wei , Po-Chao Tsao , Ching-Li Yang , Chien-Yang Chen , Hui-Ling Chen , Guan-Kai Huang
IPC分类号： H01L23/00 , H01L21/768 , H01L21/78 , H01L23/58
CPC分类号： H01L23/562 , H01L21/76838 , H01L21/78 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring.
摘要翻译：提供了模具密封环。模具密封环包括基材和从基材挤出的第一层。第一层具有第一鳍环结构，并且第一鳍环结构的布局具有戳状形状。此外，提供了一种用于形成模具密封环的方法。提供具有有源区的衬底。在衬底上形成图案化的牺牲层。在图案化牺牲层的侧壁上形成间隔物。图案化的牺牲层被去除。通过使用间隔物作为掩模对衬底进行构图，从而同时形成Fin-FET的鳍结构和模密封环的第一层。

9. 发明授权

US08841755B2 Through silicon via and method of forming the same 有权
标题翻译：通过硅通孔及其形成方法
公开(公告)号：US08841755B2
公开(公告)日：2014-09-23
申请号：US13947125
申请日：2013-07-22
申请人： United Microelectronics Corp.
发明人： Kuo-Hsiung Huang , Chun-Mao Chiou , Hsin-Yu Chen , Yu-Han Tsai , Ching-Li Yang , Home-Been Cheng
IPC分类号： H01L23/48 , H01L21/768 , H01L23/525
CPC分类号： H01L21/76843 , H01L21/76898 , H01L23/481 , H01L23/525 , H01L2224/13 , H01L2924/1461 , H01L2924/00
摘要： The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface.
摘要翻译：本发明涉及一种硅通孔（TSV）。 TSV设置在包括穿过基板的第一表面和第二表面的通孔的基板中。 TSV包括绝缘层，阻挡层，缓冲层和导电电极。绝缘层设置在通孔开口的表面上。阻挡层设置在绝缘层的表面上。缓冲层设置在阻挡层的表面上。导电电极设置在缓冲层的表面上，通孔开口的其余部分被导电电极完全填充。缓冲层的一部分还在第二表面的一侧覆盖导电电极的表面，并且所述部分与第二表面平齐。

10. 发明申请

US20150041961A1 Through silicon via structure 有权
标题翻译：通过硅通孔结构
公开(公告)号：US20150041961A1
公开(公告)日：2015-02-12
申请号：US14521456
申请日：2014-10-22
申请人： UNITED MICROELECTRONICS CORP.
发明人： Hsin-Yu Chen , Home-Been Cheng , Yu-Han Tsai , Ching-Li Yang
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L21/7684 , H01L21/76898 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via.
摘要翻译：公开了一种硅通孔结构。贯通硅通孔包括：基板; 设置在所述基板上并具有多个第一开口的第一电介质层，所述多个第一开口的底部位于比所述基板的原始表面低的位置; 设置在所述第一电介质层和所述基板上的通孔，所述通孔与所述多个第一开口全部不重叠，第二电介质层，其在填充所述多个第一开口的同时，设置在所述多个第一开口内和所述通孔的侧壁上; 以及设置在所述通孔内的导电材料层，所述导电材料层在所述通孔的侧壁上具有所述第二电介质层，从而形成通硅通孔。

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