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1. 发明申请

US20080266454A1 VIDEO SINK DEVICE 有权
标题翻译：视频SINK设备
公开(公告)号：US20080266454A1
公开(公告)日：2008-10-30
申请号：US12109868
申请日：2008-04-25
申请人： Tzuo-Bo Lin , Wen-Hsia Kung , Hsien-Chun Chang
发明人： Tzuo-Bo Lin , Wen-Hsia Kung , Hsien-Chun Chang
IPC分类号： H03L7/00 , H04N5/04
CPC分类号： H04N5/04 , H03L7/06
摘要： The invention discloses a sink device. The sink device comprises a buffering unit and a clock generating unit. The buffering unit receives a decoding data according to a symbol clock signal, reads the decoding data according to a pixel clock signal, and generates a water level value. The clock generating unit receives the symbol clock signal to generate the pixel clock signal and adjusts a rate of the pixel clock signal according to the water level value and/or a phase difference signal.
摘要翻译：本发明公开了一种信宿设备。宿设备包括缓冲单元和时钟发生单元。缓冲单元根据符号时钟信号接收解码数据，根据像素时钟信号读取解码数据，并产生水位值。时钟发生单元接收符号时钟信号以产生像素时钟信号，并根据水位值和/或相位差信号调整像素时钟信号的速率。

2. 发明授权

US08331460B2 Video sink device 有权
标题翻译：视频接收设备
公开(公告)号：US08331460B2
公开(公告)日：2012-12-11
申请号：US12109868
申请日：2008-04-25
申请人： Tzuo-Bo Lin , Wen-Hsia Kung , Hsien-Chun Chang
发明人： Tzuo-Bo Lin , Wen-Hsia Kung , Hsien-Chun Chang
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04
CPC分类号： H04N5/04 , H03L7/06
摘要： The invention discloses a sink device. The sink device comprises a buffering unit and a clock generating unit. The buffering unit receives a decoding data according to a symbol clock signal, reads the decoding data according to a pixel clock signal, and generates a water level value. The clock generating unit receives the symbol clock signal to generate the pixel clock signal and adjusts a rate of the pixel clock signal according to the water level value and/or a phase difference signal.
摘要翻译：本发明公开了一种信宿设备。宿设备包括缓冲单元和时钟发生单元。缓冲单元根据符号时钟信号接收解码数据，根据像素时钟信号读取解码数据，并产生水位值。时钟发生单元接收符号时钟信号以产生像素时钟信号，并根据水位值和/或相位差信号调整像素时钟信号的速率。

3. 发明授权

US08471859B2 Device and method for controlling frame input and output 有权
标题翻译：用于控制帧输入和输出的装置和方法
公开(公告)号：US08471859B2
公开(公告)日：2013-06-25
申请号：US12692389
申请日：2010-01-22
申请人： Chia-Lung Hung , Tzuo-Bo Lin , Hsien-Chun Chang , Yu-Pin Chou
发明人： Chia-Lung Hung , Tzuo-Bo Lin , Hsien-Chun Chang , Yu-Pin Chou
IPC分类号： G09G5/39 , G09G5/36 , G06F12/02 , H04N7/01
CPC分类号： H04N7/0105 , H04N7/0132
摘要： A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.
摘要翻译：用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。输入像素时钟不等于输出像素时钟。帧写入控制器根据输入DE和输出DE生成写许可信号。缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

4. 发明申请

US20100188574A1 DEVICE AND METHOD FOR CONTROLLING FRAME INPUT AND OUTPUT 有权
标题翻译：用于控制框架输入和输出的装置和方法
公开(公告)号：US20100188574A1
公开(公告)日：2010-07-29
申请号：US12692389
申请日：2010-01-22
申请人： Chia-Lung HUNG , Tzuo-Bo Lin , Hsien-Chun Chang , Yu-Pin Chou
发明人： Chia-Lung HUNG , Tzuo-Bo Lin , Hsien-Chun Chang , Yu-Pin Chou
IPC分类号： H04N9/64 , H04N5/04
CPC分类号： H04N7/0105 , H04N7/0132
摘要： A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.
摘要翻译：用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。输入像素时钟不等于输出像素时钟。帧写入控制器根据输入DE和输出DE生成写许可信号。缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

5. 发明授权

US07822162B2 Current mode differential signal transmitting circuit sharing a clock outputting unit 有权
标题翻译：电流模式差分信号发送电路共享时钟输出单元
公开(公告)号：US07822162B2
公开(公告)日：2010-10-26
申请号：US11627379
申请日：2007-01-26
申请人： Hsien-Chun Chang , Chao-Hsin Lu , Ming-Yen Hsu
发明人： Hsien-Chun Chang , Chao-Hsin Lu , Ming-Yen Hsu
IPC分类号： H04L7/00 , H04B3/00 , H03F3/45
CPC分类号： H04L25/0272 , H03K19/017527 , H03K19/1732
摘要： A current-mode differential signal transmitting circuit is disclosed, including a transmitter having a first transmitting module and a second transmitting module. The first transmitting module includes a plurality of first outputting units to output first data and a clock outputting signal. The second transmitting module includes a plurality of second outputting units for outputting second data, and the first and second transmitting modules share this clock outputting unit.
摘要翻译：公开了一种电流模式差分信号发射电路，包括具有第一发射模块和第二发射模块的发射机。第一发送模块包括多个第一输出单元，用于输出第一数据和时钟输出信号。第二发送模块包括用于输出第二数据的多个第二输出单元，第一和第二发送模块共享该时钟输出单元。

6. 发明申请

US20080095454A1 IMAGE ENCODING/DECODING DEVICE AND METHOD THEREOF 有权
标题翻译：图像编码/解码装置及其方法
公开(公告)号：US20080095454A1
公开(公告)日：2008-04-24
申请号：US11874214
申请日：2007-10-18
申请人： Wen-Che Wu , Hsien-Chun Chang
发明人： Wen-Che Wu , Hsien-Chun Chang
IPC分类号： G06K9/00
CPC分类号： H04N19/127 , H04N19/186 , H04N19/423
摘要： The invention provides an image encoding/decoding device and method. An encoding/decoding architecture of the invention includes: encoders for encoding image data into data blocks; a reordering multiplexer for receiving the data blocks and determining an order by which the data blocks are written into a memory according to an order of an achieved percentage of an encoding progress for each encoder; a memory writing unit, a memory dispatcher, a memory controller, and a memory reading unit, for writing the data blocks into the memory and reading the data blocks from the memory; a request demultiplexer for receiving the read data blocks from the memory reading unit and outputting the received data blocks according to data request signals; and decoders for generating the data request signals, receiving the output data blocks from the request demultiplexer, decoding the received data blocks, and then outputting the decoded data blocks.
摘要翻译：本发明提供一种图像编码/解码装置和方法。本发明的编码/解码架构包括：用于将图像数据编码成数据块的编码器; 重新排序多路复用器，用于接收数据块，并根据每个编码器的编码进程的实现百分比的顺序确定将数据块写入存储器的顺序; 存储器写入单元，存储器调度器，存储器控制器和存储器读取单元，用于将数据块写入存储器并从存储器读取数据块; 请求解复用器，用于从存储器读取单元接收读取的数据块，并根据数据请求信号输出接收到的数据块; 以及用于产生数据请求信号的解码器，从请求解复用器接收输出数据块，对接收到的数据块进行解码，然后输出解码的数据块。

7. 发明申请

US20070106835A1 Display controller and method of updating parameters of the same 有权
标题翻译：显示控制器和更新参数的方法
公开(公告)号：US20070106835A1
公开(公告)日：2007-05-10
申请号：US11594068
申请日：2006-11-08
申请人： Wen-Jui Lin , Hsien-Chun Chang , Yi-Shu Chang , Wen-Che Wu
发明人： Wen-Jui Lin , Hsien-Chun Chang , Yi-Shu Chang , Wen-Che Wu
IPC分类号： G06F12/00
CPC分类号： G06F8/65 , G09G3/2096 , G09G5/363 , G09G2320/0606 , G09G2320/08
摘要： A controller and a method of updating parameters on the same. The controller includes an embedded non-volatile memory, a programming circuit, an embedded SRAM, a MCU (Micro Computer Unit), and a memory controller. The embedded non-volatile memory has a program code block for storing program codes to be executed by the MCU, and a data block for storing the parameters. The MCU writes the parameters into the data block of the flash memory through the memory controller, or reads data in the data block of the non-volatile memory through the memory controller. Because the controller does not need to employ an external EEPROM, the cost can be reduced and the speed for accessing the parameters can be increased.
摘要翻译：控制器和更新参数的方法。控制器包括嵌入式非易失性存储器，编程电路，嵌入式SRAM，MCU（微计算机单元）和存储器控制器。嵌入式非易失性存储器具有用于存储要由MCU执行的程序代码的程序代码块和用于存储参数的数据块。 MCU通过存储器控制器将参数写入闪存的数据块，或通过存储器控制器读取非易失性存储器的数据块中的数据。由于控制器不需要使用外部EEPROM，因此可以降低成本，并且可以提高访问参数的速度。

8. 外观设计

USD516603S1 Video projector 有权
公开(公告)号：USD516603S1
公开(公告)日：2006-03-07
申请号：US29217463
申请日：2004-11-17
申请人： Ching-Lin Yeh , Cheng-Shan Lin , Yung-Chuan Ma , Chien-Jui Wang , Yung-Song Chen , Hsien-Chun Chang
设计人： Ching-Lin Yeh , Cheng-Shan Lin , Yung-Chuan Ma , Chien-Jui Wang , Yung-Song Chen , Hsien-Chun Chang

9. 发明申请

US20050160469A1 Interactive video data generating system and method thereof 审中-公开
标题翻译：交互式视频数据生成系统及其方法
公开(公告)号：US20050160469A1
公开(公告)日：2005-07-21
申请号：US10759296
申请日：2004-01-20
申请人： Chaucer Chiu , Hsien-Chun Chang
发明人： Chaucer Chiu , Hsien-Chun Chang
IPC分类号： H04N7/173 , G06F15/00 , G06F17/00 , G06F17/21
CPC分类号： H04N21/858 , H04N21/23418 , H04N21/6587 , H04N21/8545
摘要： An interactive video generating system and method allow a user to establish link relations in the video content, so that an instantaneous broadcast according to desired selections of the user can be performed. Interactive link relations between the video files are achieved by means of block locations. With this system and method, more flexibility and selectivity are allowed to the user who no longer is limited to a unidirectional fixed video broadcast sequence.
摘要翻译：交互式视频生成系统和方法允许用户在视频内容中建立链接关系，使得可以执行根据用户期望选择的即时广播。通过块位置实现视频文件之间的交互链接关系。利用该系统和方法，不再限于单向固定视频广播序列的用户允许更多的灵活性和选择性。

10. 外观设计

USD481390S1 LCD monitor 失效
公开(公告)号：USD481390S1
公开(公告)日：2003-10-28
申请号：US29166560
申请日：2002-08-28
申请人： Chien-Jui Wang , Wen-Ming Wu , Hsien-Chun Chang
设计人： Chien-Jui Wang , Wen-Ming Wu , Hsien-Chun Chang

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