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1. 发明申请

US20140027900A1 Bump Structure for Yield Improvement 有权
标题翻译：膨胀结构产量提高
公开(公告)号：US20140027900A1
公开(公告)日：2014-01-30
申请号：US13558082
申请日：2012-07-25
申请人： Tzu-Wei Chiu , Tzu-Yu Wang , Shang-Yun Hou , Shin-Puu Jeng , Hsien-Wei Chen , Hung-An Teng , Wei-Cheng Wu
发明人： Tzu-Wei Chiu , Tzu-Yu Wang , Shang-Yun Hou , Shin-Puu Jeng , Hsien-Wei Chen , Hung-An Teng , Wei-Cheng Wu
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L24/81 , B23K1/0016 , C23C14/165 , C23C14/34 , C23C18/32 , C23C18/42 , H01L23/3192 , H01L23/562 , H01L24/11 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/10125 , H01L2224/114 , H01L2224/1145 , H01L2224/1146 , H01L2224/1147 , H01L2224/119 , H01L2224/11903 , H01L2224/13005 , H01L2224/13012 , H01L2224/13019 , H01L2224/13022 , H01L2224/13076 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13166 , H01L2224/13562 , H01L2224/13564 , H01L2224/13583 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2224/16058 , H01L2224/16059 , H01L2224/16145 , H01L2224/16148 , H01L2224/8112 , H01L2224/81141 , H01L2224/81193 , H01L2224/81345 , H01L2224/81365 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06593 , H01L2924/00014 , H01L2924/014 , H01L2924/13091 , H01L2224/81 , H01L2924/00012 , H01L2924/207 , H01L2924/206 , H01L2224/05552 , H01L2924/00
摘要： A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.
摘要翻译：提供了用于电耦合半导体部件的凸块结构。凸块结构包括在第一半导体部件上的第一凸块和第二半导体部件上的第二凸块。第一凸起具有第一非平坦部分（例如，凸起的凸起），并且第二凸起具有第二非平坦部分（例如，凹形凹部）。凸起结构还包括形成在第一和第二非平坦部分之间的焊接接头以电耦合半导体部件。

2. 发明授权

US09553053B2 Bump structure for yield improvement 有权
标题翻译：膨胀结构用于产量提高
公开(公告)号：US09553053B2
公开(公告)日：2017-01-24
申请号：US13558082
申请日：2012-07-25
申请人： Tzu-Wei Chiu , Tzu-Yu Wang , Shang-Yun Hou , Shin-Puu Jeng , Hsien-Wei Chen , Hung-An Teng , Wei-Cheng Wu
发明人： Tzu-Wei Chiu , Tzu-Yu Wang , Shang-Yun Hou , Shin-Puu Jeng , Hsien-Wei Chen , Hung-An Teng , Wei-Cheng Wu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/00 , H01L23/31
CPC分类号： H01L24/81 , B23K1/0016 , C23C14/165 , C23C14/34 , C23C18/32 , C23C18/42 , H01L23/3192 , H01L23/562 , H01L24/11 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/10125 , H01L2224/114 , H01L2224/1145 , H01L2224/1146 , H01L2224/1147 , H01L2224/119 , H01L2224/11903 , H01L2224/13005 , H01L2224/13012 , H01L2224/13019 , H01L2224/13022 , H01L2224/13076 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13166 , H01L2224/13562 , H01L2224/13564 , H01L2224/13583 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2224/16058 , H01L2224/16059 , H01L2224/16145 , H01L2224/16148 , H01L2224/8112 , H01L2224/81141 , H01L2224/81193 , H01L2224/81345 , H01L2224/81365 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06593 , H01L2924/00014 , H01L2924/014 , H01L2924/13091 , H01L2224/81 , H01L2924/00012 , H01L2924/207 , H01L2924/206 , H01L2224/05552 , H01L2924/00
摘要： A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.
摘要翻译：提供了用于电耦合半导体部件的凸块结构。凸块结构包括在第一半导体部件上的第一凸块和第二半导体部件上的第二凸块。第一凸起具有第一非平坦部分（例如，凸起的凸起），并且第二凸起具有第二非平坦部分（例如，凹形凹部）。凸起结构还包括形成在第一和第二非平坦部分之间的焊接接头以电耦合半导体部件。

3. 发明授权

US08558229B2 Passivation layer for packaged chip 有权
标题翻译：封装芯片的钝化层
公开(公告)号：US08558229B2
公开(公告)日：2013-10-15
申请号：US13313747
申请日：2011-12-07
申请人： Shin-Puu Jeng , Wei-Cheng Wu , Shang-Yun Hou , Chen-Hua Yu , Tzuan-Horng Liu , Tzu-Wei Chiu , Kuo-Ching Hsu
发明人： Shin-Puu Jeng , Wei-Cheng Wu , Shang-Yun Hou , Chen-Hua Yu , Tzuan-Horng Liu , Tzu-Wei Chiu , Kuo-Ching Hsu
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , G01R31/2884 , H01L21/76885 , H01L22/32 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/02126 , H01L2224/0401 , H01L2224/05001 , H01L2224/0554 , H01L2224/10126 , H01L2224/13005 , H01L2224/16225 , H01L2924/12044 , H01L2924/15311 , H01L2924/00
摘要： The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.
摘要翻译：上述实施例提供了在封装的集成电路（IC）芯片上用测试焊盘在金属焊盘上形成金属凸块的机构。形成钝化层以覆盖测试焊盘和可能的金属焊盘部分。钝化层不覆盖远离测试焊盘区域和金属焊盘区域的表面。通过钝化层测试焊盘和金属焊盘部分的有限覆盖减少了形成在金属焊盘和金属凸块之间的UBM层的界面电阻。这种界面电阻的降低导致金属凸块的电阻降低。

4. 发明授权

US08283781B2 Semiconductor device having pad structure with stress buffer layer 有权
标题翻译：具有应力缓冲层的衬垫结构的半导体器件
公开(公告)号：US08283781B2
公开(公告)日：2012-10-09
申请号：US12879512
申请日：2010-09-10
申请人： Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng , Tzuan-Horng Liu , Tzu-Wei Chiu , Chao-Wen Shih
发明人： Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng , Tzuan-Horng Liu , Tzu-Wei Chiu , Chao-Wen Shih
IPC分类号： H01L29/40
CPC分类号： H01L24/11 , H01L23/3114 , H01L23/3157 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02126 , H01L2224/0235 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05005 , H01L2224/05008 , H01L2224/05012 , H01L2224/05014 , H01L2224/05015 , H01L2224/05018 , H01L2224/05022 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05541 , H01L2224/05558 , H01L2224/05559 , H01L2224/05562 , H01L2224/05572 , H01L2224/05573 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05687 , H01L2224/06131 , H01L2224/10126 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/1308 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/94 , H01L2924/00014 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/35 , H01L2924/3512 , H01L2924/35121 , H01L2224/03 , H01L2224/11 , H01L2924/04941 , H01L2924/04953 , H01L2924/01028 , H01L2924/01022 , H01L2924/01083 , H01L2924/01051 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.
摘要翻译：半导体器件具有在金属焊盘和凸块下金属化（UBM）层之间具有环形应力缓冲层的焊盘结构。应力缓冲层由介电常数小于3.5的介质层，聚合物层或铝层形成。应力缓冲层是圆形环，方形环，八角形环或任何其它几何环。

5. 发明申请

US20130113070A1 Interposers for Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件的插入件及其制造方法
公开(公告)号：US20130113070A1
公开(公告)日：2013-05-09
申请号：US13292792
申请日：2011-11-09
申请人： Tzu-Wei Chiu , Tzu-Yu Wang , Wei-Cheng Wu , Chun-Yi Liu , Hsien-Pin Hu , Shang-Yun Hou
发明人： Tzu-Wei Chiu , Tzu-Yu Wang , Wei-Cheng Wu , Chun-Yi Liu , Hsien-Pin Hu , Shang-Yun Hou
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/49827 , H01L23/3128 , H01L23/481 , H01L23/525 , H01L23/5256 , H01L23/5382 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/13184 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81192 , H01L2924/00011 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2924/157 , H01L2924/00 , H01L2224/81805
摘要： Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via.
摘要翻译：公开了半导体器件用插入件及其制造方法。在一个实施例中，插入器包括衬底，设置在衬底上的接触焊盘以及耦合到接触焊盘的衬底中的第一通孔。第一保险丝耦合到第一通孔。衬底中的第二通孔耦合到接触焊盘，并且第二保险丝耦合到第二通孔。

6. 发明授权

US08896089B2 Interposers for semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件用插入件及其制造方法
公开(公告)号：US08896089B2
公开(公告)日：2014-11-25
申请号：US13292792
申请日：2011-11-09
申请人： Tzu-Wei Chiu , Tzu-Yu Wang , Wei-Cheng Wu , Chun-Yi Liu , Hsien-Pin Hu , Shang-Yun Hou
发明人： Tzu-Wei Chiu , Tzu-Yu Wang , Wei-Cheng Wu , Chun-Yi Liu , Hsien-Pin Hu , Shang-Yun Hou
IPC分类号： H01L23/52 , H01L21/82 , H01L23/498 , H01L23/538 , H01L23/00 , H01L23/525 , H01L23/48 , H01L23/31
CPC分类号： H01L23/49827 , H01L23/3128 , H01L23/481 , H01L23/525 , H01L23/5256 , H01L23/5382 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/13184 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81192 , H01L2924/00011 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2924/157 , H01L2924/00 , H01L2224/81805
摘要： Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via.
摘要翻译：公开了半导体器件用插入件及其制造方法。在一个实施例中，插入器包括衬底，设置在衬底上的接触焊盘以及耦合到接触焊盘的衬底中的第一通孔。第一保险丝耦合到第一通孔。衬底中的第二通孔耦合到接触焊盘，并且第二保险丝耦合到第二通孔。

7. 发明申请

US20110186987A1 STRESS BUFFER STRUCTURES IN A MOUNTING STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件的安装结构中的应力缓冲结构及其制造方法
公开(公告)号：US20110186987A1
公开(公告)日：2011-08-04
申请号：US12697473
申请日：2010-02-01
申请人： Tzu-Yu Wang , Tzu-Wei Chiu , Shin-Puu Jeng
发明人： Tzu-Yu Wang , Tzu-Wei Chiu , Shin-Puu Jeng
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L23/3192 , H01L21/76804 , H01L21/76885 , H01L23/293 , H01L23/31 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/0215 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05558 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05684 , H01L2224/10156 , H01L2224/131 , H01L2224/81815 , H01L2924/00014 , H01L2924/0002 , H01L2924/14 , H01L2924/351 , H01L2924/06 , H01L2924/00012 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： A mounting structure for a semiconductor device includes a stepwise stress buffer layer under a likewise stepwise UBM structure.
摘要翻译：半导体器件的安装结构包括在同样的逐步UBM结构下的逐步应力缓冲层。

8. 发明授权

US08354750B2 Stress buffer structures in a mounting structure of a semiconductor device 有权
标题翻译：半导体器件的安装结构中的应力缓冲结构
公开(公告)号：US08354750B2
公开(公告)日：2013-01-15
申请号：US12697473
申请日：2010-02-01
申请人： Tzu-Yu Wang , Tzu-Wei Chiu , Shin-Puu Jeng
发明人： Tzu-Yu Wang , Tzu-Wei Chiu , Shin-Puu Jeng
IPC分类号： H01L23/498
CPC分类号： H01L23/3192 , H01L21/76804 , H01L21/76885 , H01L23/293 , H01L23/31 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/0215 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05558 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05684 , H01L2224/10156 , H01L2224/131 , H01L2224/81815 , H01L2924/00014 , H01L2924/0002 , H01L2924/14 , H01L2924/351 , H01L2924/06 , H01L2924/00012 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： A mounting structure for a semiconductor device includes a stepwise stress buffer layer under a likewise stepwise UBM structure.
摘要翻译：半导体器件的安装结构包括在同样的逐步UBM结构下的逐步应力缓冲层。

9. 发明授权

US08587089B2 Seal ring structure with polyimide layer adhesion 有权
标题翻译：密封圈结构与聚酰亚胺层粘合
公开(公告)号：US08587089B2
公开(公告)日：2013-11-19
申请号：US12938680
申请日：2010-11-03
申请人： Tzu-Wei Chiu
发明人： Tzu-Wei Chiu
IPC分类号： H01L23/52
CPC分类号： H01L23/3192 , H01L23/10 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a semiconductor device, including a substrate having a seal ring region and a circuit region, a seal ring structure disposed over the seal ring region, a first passivation layer disposed over the seal ring structure, the first passivation layer having a first passivation layer aperture over the seal ring structure, and a metal pad disposed over the first passivation layer, the metal pad coupled to the seal ring structure through the first passivation layer aperture and having a metal pad aperture above the first passivation layer aperture. The device further includes a second passivation layer disposed over the metal pad, the second passivation layer having a second passivation layer aperture above the metal pad aperture, and a polyimide layer disposed over the second passivation layer, the polyimide layer filling the second passivation layer aperture to form a polyimide root at an exterior tapered edge of the polyimide layer.
摘要翻译：本公开提供一种半导体器件，包括具有密封环区域和电路区域的衬底，设置在密封环区域上方的密封环结构，设置在密封环结构上方的第一钝化层，第一钝化层具有第一在密封环结构上方的钝化层孔，以及设置在第一钝化层之上的金属焊盘，金属焊盘通过第一钝化层孔耦合到密封环结构，并且在第一钝化层孔的上方具有金属焊盘孔。该器件还包括设置在金属焊盘上的第二钝化层，第二钝化层在金属焊盘孔上方具有第二钝化层孔，以及设置在第二钝化层之上的聚酰亚胺层，聚酰亚胺层填充第二钝化层孔以在聚酰亚胺层的外部锥形边缘处形成聚酰亚胺根。

10. 发明申请

US20120104541A1 SEAL RING STRUCTURE WITH POLYIMIDE LAYER ADHESION 有权
标题翻译：密封环结构与聚酰亚胺粘合
公开(公告)号：US20120104541A1
公开(公告)日：2012-05-03
申请号：US12938680
申请日：2010-11-03
申请人： Tzu-Wei Chiu
发明人： Tzu-Wei Chiu
IPC分类号： H01L27/04 , H01L21/28
CPC分类号： H01L23/3192 , H01L23/10 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a semiconductor device, including a substrate having a seal ring region and a circuit region, a seal ring structure disposed over the seal ring region, a first passivation layer disposed over the seal ring structure, the first passivation layer having a first passivation layer aperture over the seal ring structure, and a metal pad disposed over the first passivation layer, the metal pad coupled to the seal ring structure through the first passivation layer aperture and having a metal pad aperture above the first passivation layer aperture. The device further includes a second passivation layer disposed over the metal pad, the second passivation layer having a second passivation layer aperture above the metal pad aperture, and a polyimide layer disposed over the second passivation layer, the polyimide layer filling the second passivation layer aperture to form a polyimide root at an exterior tapered edge of the polyimide layer.
摘要翻译：本公开提供一种半导体器件，包括具有密封环区域和电路区域的衬底，设置在密封环区域上方的密封环结构，设置在密封环结构上方的第一钝化层，第一钝化层具有第一在密封环结构上方的钝化层孔，以及设置在第一钝化层之上的金属焊盘，金属焊盘通过第一钝化层孔耦合到密封环结构，并且在第一钝化层孔的上方具有金属焊盘孔。该器件还包括设置在金属焊盘上的第二钝化层，第二钝化层在金属焊盘孔上方具有第二钝化层孔，以及设置在第二钝化层之上的聚酰亚胺层，聚酰亚胺层填充第二钝化层孔以在聚酰亚胺层的外部锥形边缘处形成聚酰亚胺根。

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