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1. 发明申请

US20100315374A1 DISPLAY DEVICE AND METHOD OF APPLYING THE SAME 审中-公开
标题翻译：显示装置及其应用方法
公开(公告)号：US20100315374A1
公开(公告)日：2010-12-16
申请号：US12764095
申请日：2010-04-21
申请人： Tzu-Jung Chen , Po-Yuan Liu , Min-Feng Chiang , Ming-Sheng Lai
发明人： Tzu-Jung Chen , Po-Yuan Liu , Min-Feng Chiang , Ming-Sheng Lai
IPC分类号： G06F3/045
CPC分类号： G06F3/044
摘要： A display device and a method of applying the same are introduced herein. A shielding layer is utilized to interpose between a transparent conductive layer of a touch element and a common electrode layer of a liquid crystal display (LCD) panel. With controlling variances of a first and a second control signals, a coupling current between the transparent conductive layer and common electrode layer can approach none, whereby influences of capacitive coupling effect between the common electrode layer or shielding layer and the transparent conductive layer of the touch element can be reduced. Thus, high touch accuracy of the touch element can be achieved and the noise can be eliminated simultaneously.
摘要翻译：介绍了显示装置及其应用方法。屏蔽层用于插入触摸元件的透明导电层和液晶显示器（LCD）面板的公共电极层之间。利用第一和第二控制信号的控制方差，透明导电层和公共电极层之间的耦合电流可以不接近，由此在公共电极层或屏蔽层与触摸的透明导电层之间的电容耦合效应的影响元素可以减少。因此，可以实现触摸元件的高触摸精度并且可以同时消除噪声。

2. 发明申请

US20090146981A1 LIGHT DETECTION SYSTEM AND RELATED METHOD 审中-公开
标题翻译：光检测系统及相关方法
公开(公告)号：US20090146981A1
公开(公告)日：2009-06-11
申请号：US12104449
申请日：2008-04-17
申请人： Chi-Wen Chen , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Chi-Wen Chen , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G09G5/00
CPC分类号： G09G3/3406 , G09G2320/064 , G09G2360/144
摘要： The present invention provides a light detection system essentially including a light detection circuit for generating a light detection signal by performing a light detection process, an integration-period control circuit for generating a control signal based on the light detection signal, and an integration circuit for adjusting an integration period based on the control signal and generating a readout signal by performing an integration process on the light detection signal during the adjusted integration period. The present invention further provides a light detection method essentially including providing a plurality of integration periods, generating a light detection signal by performing a light detection process, selecting an integration period out of the provided integration periods based on the light detection signal, and generating a readout signal by performing an integration process on the light detection signal during the selected integration period.
摘要翻译：本发明提供一种光检测系统，其基本上包括：通过执行光检测处理产生光检测信号的光检测电路;基于光检测信号产生控制信号的积分周期控制电路;以及用于基于所述控制信号调整积分期间，并通过在调整后的积分期间对所述光检测信号进行积分处理来生成读出信号。本发明还提供了一种光检测方法，其基本上包括提供多个积分周期，通过执行光检测处理产生光检测信号，基于光检测信号从提供的积分周期中选择积分期，并产生在所选择的积分期间对光检测信号进行积分处理。

3. 发明申请

US20110158376A1 SHIFT REGISTER 有权
公开(公告)号：US20110158376A1
公开(公告)日：2011-06-30
申请号：US13041794
申请日：2011-03-07
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/34
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.

4. 发明授权

US07924967B2 Shift register 有权
公开(公告)号：US07924967B2
公开(公告)日：2011-04-12
申请号：US12877748
申请日：2010-09-08
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.

5. 发明授权

US08031827B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08031827B2
公开(公告)日：2011-10-04
申请号：US13041794
申请日：2011-03-07
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
摘要翻译：移位寄存器包括多个级，{Sn}，n = 1,2。。。，N，N为正整数。在一个实施例中，每级Sn包括一个上拉电路，该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端，用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时，上拉控制电路响应地产生提供给输入节点Qn的信号，以接通上拉电路，电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路，以及被配置为接收一个电压的下拉控制电路第三时钟信号CK2和第四时钟信号XCK2，并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和阶段Sn + 1。

6. 发明申请

US20110007863A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20110007863A1
公开(公告)日：2011-01-13
申请号：US12877748
申请日：2010-09-08
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
摘要翻译：移位寄存器包括多个级，{Sn}，n = 1,2。。。，N，N为正整数。在一个实施例中，每级Sn包括一个上拉电路，该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端，用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时，上拉控制电路响应地产生提供给输入节点Qn的信号，以接通上拉电路，电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路，以及被配置为接收一个电压的下拉控制电路第三时钟信号CK2和第四时钟信号XCK2，并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和阶段Sn + 1。

7. 发明授权

US07817771B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US07817771B2
公开(公告)日：2010-10-19
申请号：US12334874
申请日：2008-12-15
申请人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
发明人： Tsung-Ting Tsai , Ming-Sheng Lai , Min-Feng Chiang , Po-Yuan Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.
摘要翻译：移位寄存器包括多个级，{Sn}，n = 1,2。。。，N，N为正整数。在一个实施例中，每级Sn包括一个上拉电路，该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端，用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时，上拉控制电路响应地产生提供给输入节点Qn的信号，以接通上拉电路，电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路，以及被配置为接收一个电压的下拉控制电路第三时钟信号CK2和第四时钟信号XCK2，并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和阶段Sn + 1。

8. 发明申请

US20090243981A1 Driving module of display device and method for extending lifetime of the driving module 审中-公开
标题翻译：显示装置的驱动模块和延长驱动模块寿命的方法
公开(公告)号：US20090243981A1
公开(公告)日：2009-10-01
申请号：US12185821
申请日：2008-08-05
申请人： Yung-Chih Chen , Chun-Hsin Liu , Po-Yuan Liu , Min-Feng Chiang
发明人： Yung-Chih Chen , Chun-Hsin Liu , Po-Yuan Liu , Min-Feng Chiang
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/006 , G09G2330/08
摘要： A driving module drives a display device having a plurality of pixel switches. The driving module includes a gate driving circuit, a plurality of switch components, and a shorting line. The gate driving circuit includes a plurality of output ends correspondingly coupled to the plurality of the pixel switches through a plurality of gate lines for outputting a plurality of gate driving signals and turning on the plurality of the pixel switches. The plurality of the gate lines are coupled to the shorting line through the switch components. Each control end of the switch components is coupled to the gate driving circuit for receiving the gate driving signals in order to refresh the state of the switch components.
摘要翻译：驱动模块驱动具有多个像素开关的显示装置。驱动模块包括栅极驱动电路，多个开关部件和短路线。栅极驱动电路包括通过多条栅极线对应地耦合到多个像素开关的多个输出端，用于输出多个栅极驱动信号并导通多个像素开关。多个栅极线通过开关部件耦合到短路线。开关部件的每个控制端耦合到栅极驱动电路，用于接收栅极驱动信号，以刷新开关部件的状态。

9. 发明申请

US20110037688A1 Liquid Crystal Display and Operation Method Thereof 有权
公开(公告)号：US20110037688A1
公开(公告)日：2011-02-17
申请号：US12912230
申请日：2010-10-26
申请人： Min-Feng Chiang , Hsueh-Ying Huang , Ming-Sheng Lai
发明人： Min-Feng Chiang , Hsueh-Ying Huang , Ming-Sheng Lai
IPC分类号： G09G3/36
CPC分类号： G09G3/3659 , G02F1/13624 , G02F2001/134345 , G09G2300/0443 , G09G2300/0447 , G09G2310/0205 , G09G2320/028
摘要： A pixel unit in the present invention is divided into two sub-pixels. Each sub-pixel includes a thin film transistor, a liquid crystal capacitor and a storage capacitor. The two transistors respectively located in different sub-pixels are connected to different scan lines. One of the two transistors is connected to the data line through another transistor. Therefore, two different pixel voltages are formed in a pixel.

10. 发明授权

US07142261B2 Liquid crystal display having compensation capacitor 有权
标题翻译：具有补偿电容器的液晶显示器
公开(公告)号：US07142261B2
公开(公告)日：2006-11-28
申请号：US10881829
申请日：2004-06-29
申请人： Min-Feng Chiang , Ming-Sheng Lai , Kuo-Hsing Cheng , I-Fang Wang , Yan-Sian Ye
发明人： Min-Feng Chiang , Ming-Sheng Lai , Kuo-Hsing Cheng , I-Fang Wang , Yan-Sian Ye
IPC分类号： G02F1/1343 , H01L29/04
CPC分类号： G02F1/136213 , G02F1/136286 , G02F2001/13606
摘要： A liquid crystal display includes a pixel electrode coupled in each of a plurality of pixels, wherein the pixel electrode has a first side along which runs a first data line and a second side along which runs a second data line, and a switch element coupling the pixel electrode with one scan line and the first data line. A conductive layer is connected to any of the first or second data line to form a compensation capacitor coupling between the pixel electrode and the first or second data line. The compensation capacitor balances the capacitive coupling at the two sides of the pixel electrode adjacent to the first and second side of the pixel electrode.
摘要翻译：液晶显示器包括耦合在多个像素中的每一个中的像素电极，其中像素电极具有第一侧，第一侧沿着第一数据线和第二侧沿第一数据线运行，第二侧运行第二数据线;以及开关元件，具有一条扫描线和第一条数据线的像素电极。导电层连接到第一或第二数据线中的任一个，以形成在像素电极和第一或第二数据线之间耦合的补偿电容。补偿电容器平衡与像素电极的第一和第二侧相邻的像素电极的两侧的电容耦合。

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