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1. 发明申请

US20100031073A1 SYSTEMS AND METHODS FOR POWER MANAGEMENT IN ELECTRONIC DEVICES 有权
标题翻译：电子设备电源管理系统与方法
公开(公告)号：US20100031073A1
公开(公告)日：2010-02-04
申请号：US12184987
申请日：2008-08-01
申请人： Tzong-Kwang Henry Yeh , Tak Kwong Wong
发明人： Tzong-Kwang Henry Yeh , Tak Kwong Wong
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： Systems and methods are disclosed for managing power consumption in electronic devices. In certain embodiments, an integrated circuit for managing power consumption in an electronic device includes an input/output (I/O) interface, a first circuit block coupled to the I/O interface, and an interface circuit coupled between the I/O interface and the first circuit block, the interface circuit configured to provide a defined logic state to the first circuit block or a second circuit block external to the integrated circuit if one of the first circuit block or the second circuit block is powered down. By providing a defined logic state to the first circuit block or the second circuit block when one of the first circuit block or the second circuit block is powered down, power consumption of the electronic device may be reduced.
摘要翻译：公开了用于管理电子设备中的功耗的系统和方法。在某些实施例中，用于管理电子设备中的功耗的集成电路包括输入/输出（I / O）接口，耦合到I / O接口的第一电路块，以及耦合在I / O接口以及所述第一电路块，所述接口电路被配置为：如果所述第一电路块或所述第二电路块中的一个被掉电，则将限定的逻辑状态提供给所述第一电路块或所述集成电路外部的第二电路块。当第一电路块或第二电路块中的一个被断电时，通过向第一电路块或第二电路块提供定义的逻辑状态，可以减少电子设备的功耗。

2. 发明授权

US08892930B2 Systems and methods for power management in electronic devices 有权
标题翻译：电子设备电源管理系统和方法
公开(公告)号：US08892930B2
公开(公告)日：2014-11-18
申请号：US12184987
申请日：2008-08-01
申请人： Tzong-Kwang Henry Yeh , Tak Kwong Wong
发明人： Tzong-Kwang Henry Yeh , Tak Kwong Wong
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： Systems and methods are disclosed for managing power consumption in electronic devices. In certain embodiments, an integrated circuit for managing power consumption in an electronic device includes an input/output (I/O) interface, a first circuit block coupled to the I/O interface, and an interface circuit coupled between the I/O interface and the first circuit block, the interface circuit configured to provide a defined logic state to the first circuit block or a second circuit block external to the integrated circuit if one of the first circuit block or the second circuit block is powered down. By providing a defined logic state to the first circuit block or the second circuit block when one of the first circuit block or the second circuit block is powered down, power consumption of the electronic device may be reduced.
摘要翻译：公开了用于管理电子设备中的功耗的系统和方法。在某些实施例中，用于管理电子设备中的功耗的集成电路包括输入/输出（I / O）接口，耦合到I / O接口的第一电路块，以及耦合在I / O接口以及所述第一电路块，所述接口电路被配置为：如果所述第一电路块或所述第二电路块中的一个被掉电，则将限定的逻辑状态提供给所述第一电路块或所述集成电路外部的第二电路块。当第一电路块或第二电路块中的一个被断电时，通过向第一电路块或第二电路块提供定义的逻辑状态，可以减少电子设备的功耗。

3. 发明授权

US07747828B2 Systems and methods for monitoring and controlling binary state devices using a memory device 有权
标题翻译：使用存储设备监控和控制二进制状态设备的系统和方法
公开(公告)号：US07747828B2
公开(公告)日：2010-06-29
申请号：US10992428
申请日：2004-11-17
申请人： Yunsheng Wang , Casey Springer , Tak Kwong Wong , Bill Beane
发明人： Yunsheng Wang , Casey Springer , Tak Kwong Wong , Bill Beane
IPC分类号： G06F13/20
CPC分类号： G11C7/1075 , G06F13/1663
摘要： A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.
摘要翻译：静态随机存取存储器（SRAM）包括用于监视外部二进制器件状态的输入读寄存器（IRR）和用于控制外部二进制器件状态的输出驱动寄存器（ODR）。 SRAM可以是多端口设备，用于多个处理器或控制器的访问。 IRR的每一位可以反映连接的外部二进制设备的状态，并可以使用标准读取指令读取到连接的处理器。 ODR的每一位可以通过为器件提供SRAM电源电压的路径来操纵连接的外部二进制器件的状态。也可以在不改变连接的外部二进制设备的状态或中断操作的情况下读取ODR的每个位。当设置为正确模式时，用于IRR和ODR的地址可以与SRAM主存储器阵列一起用于标准存储器操作。

4. 发明授权

US07688105B2 Impedance matching logic 有权
标题翻译：阻抗匹配逻辑
公开(公告)号：US07688105B2
公开(公告)日：2010-03-30
申请号：US12170012
申请日：2008-07-09
申请人： Tak Kwong Wong
发明人： Tak Kwong Wong
IPC分类号： H03K17/16
CPC分类号： H04L25/0278
摘要： An impedance matching logic generates code values that define pull-up and pull-down transistors to be enabled with output buffers. The output buffers store the code values using a two-stage latch configuration, such that updated code values are always stored within the output buffer, even if the output buffer is driving an output signal when the updated code values are received. The impedance matching logic uses previously determined code values to shorten the time required to calculate updated code values. The impedance matching logic may be operated in response to a clock signal having a frequency lower than the frequency of the output clock signal used to control the output buffers. The impedance matching logic may adjust the code values by certain percentages using a multiplication function, thereby allowing for design fine tuning (e.g., due to layout mismatch).
摘要翻译：阻抗匹配逻辑产生定义上拉和下拉晶体管的代码值，以使能输出缓冲器。输出缓冲器使用两级锁存器配置来存储代码值，使得更新的代码值总是存储在输出缓冲器内，即使当接收到更新的代码值时输出缓冲器正在驱动输出信号。阻抗匹配逻辑使用先前确定的代码值来缩短计算更新代码值所需的时间。阻抗匹配逻辑可以响应于具有低于用于控制输出缓冲器的输出时钟信号的频率的时钟信号来操作。阻抗匹配逻辑可以使用乘法函数来调整代码值一定百分比，从而允许设计精调（例如，由于布局不匹配）。

5. 发明授权

US07898288B2 Input termination for delay locked loop feedback with impedance matching 有权
标题翻译：具有阻抗匹配的延迟锁定环路反馈的输入端接
公开(公告)号：US07898288B2
公开(公告)日：2011-03-01
申请号：US11608234
申请日：2006-12-07
申请人： Tak Kwong Wong
发明人： Tak Kwong Wong
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03L7/0812
摘要： A reference output circuit for generating an output clock signal for driving signals off of an integrated circuit chip uses a switched terminated load in combination with an output buffer to generate a feedback clock signal, which is used, in combination with a reference input clock signal, to generate the output clock signal. The switched terminated load uses transistors having the same size as transistors in the output buffer. The switched terminated load draws the same DC current as the output buffer. As a result, the switched terminated load and the output buffer have the same electro-migration performance. Pull-up and pull-down MOS impedances of the switched terminated load are easily adjusted during switching periods of the switched terminated load. The design of the switched terminated load minimizes variations in the terminated load impedance due to MOS impedance variations.
摘要翻译：用于产生用于驱动集成电路芯片的信号的输出时钟信号的参考输出电路使用结合输出缓冲器的开关端接负载来产生与参考输入时钟信号结合使用的反馈时钟信号，以产生输出时钟信号。开关端接负载使用与输出缓冲器中的晶体管尺寸相同的晶体管。开关端接负载与输出缓冲器相同的直流电流。结果，开关端接负载和输出缓冲器具有相同的电迁移性能。开关端接负载的上拉下拉MOS阻抗在开关端接负载的切换期间容易调整。开关端接负载的设计最小化由于MOS阻抗变化引起的端接负载阻抗的变化。

6. 发明申请

US20080168256A1 Modular Distributive Arithmetic Logic Unit 有权
标题翻译：模块化分布式算术逻辑单元
公开(公告)号：US20080168256A1
公开(公告)日：2008-07-10
申请号：US11621105
申请日：2007-01-08
申请人： Tak Kwong Wong
发明人： Tak Kwong Wong
IPC分类号： G06F15/76 , G06F13/00 , G06F12/02 , G06F9/30
CPC分类号： G06F9/3824 , G06F9/30014 , G06F9/3004 , G06F9/30101 , G06F9/3879 , G06F15/7821
摘要： A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is stored in a corresponding one of the memory blocks. In a read-modify-write operation, each byte of the data value is read from the corresponding memory block, and is provided to the corresponding ALU. Similarly, each byte of a modify data value is provided to a corresponding ALU on a memory data bus. Each ALU combines the read byte with the modify byte to create a write byte. Because the write bytes are all generated locally within the ALUs, long signal delay paths are avoided. Each ALU also generates two possible carry bits in parallel, and then uses the actual received carry bit to select from the two possible carry bits.
摘要翻译：存储器系统包括多个存储块，每个存储块具有专用的本地算术逻辑单元（ALU）。存储具有多个字节的数据值，使得每个字节被存储在对应的一个存储块中。在读 - 修改 - 写操作中，数据值的每个字节从对应的存储块读取，并提供给相应的ALU。类似地，将修改数据值的每个字节提供给存储器数据总线上的相应ALU。每个ALU将读取字节与修改字节组合以创建写入字节。由于写入字节全部在ALU内本地生成，因此避免了长信号延迟路径。每个ALU还并行生成两个可能的进位，然后使用实际的接收进位来从两个可能的进位中进行选择。

7. 发明申请

US20080136443A1 Input Termination For Delay Locked Loop Feedback With Impedance Matching 有权
标题翻译：具有阻抗匹配的延迟锁定环路反馈的输入端接
公开(公告)号：US20080136443A1
公开(公告)日：2008-06-12
申请号：US11608234
申请日：2006-12-07
申请人： Tak Kwong Wong
发明人： Tak Kwong Wong
IPC分类号： H03K19/003 , H03K3/00
CPC分类号： H03K19/0005 , H03L7/0812
摘要： A reference output circuit for generating an output clock signal for driving signals off of an integrated circuit chip uses a switched terminated load in combination with an output buffer to generate a feedback clock signal, which is used, in combination with a reference input clock signal, to generate the output clock signal. The switched terminated load uses transistors having the same size as transistors in the output buffer. The switched terminated load draws the same DC current as the output buffer. As a result, the switched terminated load and the output buffer have the same electro-migration performance. Pull-up and pull-down MOS impedances of the switched terminated load are easily adjusted during switching periods of the switched terminated load. The design of the switched terminated load minimizes variations in the terminated load impedance due to MOS impedance variations.
摘要翻译：用于产生用于驱动集成电路芯片的信号的输出时钟信号的参考输出电路使用结合输出缓冲器的开关端接负载来产生与参考输入时钟信号结合使用的反馈时钟信号，以产生输出时钟信号。开关端接负载使用与输出缓冲器中的晶体管尺寸相同的晶体管。开关端接负载与输出缓冲器相同的直流电流。结果，开关端接负载和输出缓冲器具有相同的电迁移性能。开关端接负载的上拉下拉MOS阻抗在开关端接负载的切换期间容易调整。开关端接负载的设计最小化由于MOS阻抗变化引起的端接负载阻抗的变化。

8. 发明授权

US07162673B2 Scan chain registers that utilize feedback paths within latch units to support toggling of latch unit outputs during enhanced delay fault testing 有权
标题翻译：扫描链寄存器利用锁存单元内的反馈路径支持在增强延迟故障测试期间切换锁存单元输出
公开(公告)号：US07162673B2
公开(公告)日：2007-01-09
申请号：US10933772
申请日：2004-09-03
申请人： Tak Kwong Wong
发明人： Tak Kwong Wong
IPC分类号： G01R31/28
CPC分类号： G01R31/31858 , G01R31/318541
摘要： An integrated circuit device utilizes a serial scan chain register to support efficient reliability testing of internal circuitry that is not readily accessible from the I/O pins of the device. The scan chain register has scan chain latch units that support a toggle mode of operation. The scan chain register is provided with serial and parallel input ports and serial and parallel output ports. Each of the plurality of scan chain latch units includes a latch element and additional circuit elements that are configured to selectively establish a feedback path in the respective latch unit. This feedback path operates to pass an inversion of a signal at an output of the latch to an input of the latch when the corresponding scan chain latch unit is enabled to support a toggle mode of operation.
摘要翻译：集成电路器件利用串行扫描链寄存器来支持内部电路的高效可靠性测试，该器件不容易从器件的I / O引脚访问。扫描链寄存器具有支持切换操作模式的扫描链锁定单元。扫描链寄存器配有串行和并行输入端口以及串行和并行输出端口。多个扫描链锁定单元中的每一个包括锁存元件和被配置为在相应的锁存单元中选择性地建立反馈路径的附加电路元件。当对应的扫描链锁定单元被启用以支持切换操作模式时，该反馈路径用于将锁存器的输出处的信号的反相传递到锁存器的输入。

9. 发明授权

US07904667B2 Systems and methods for monitoring and controlling binary state devices using a memory device 失效
标题翻译：使用存储设备监控和控制二进制状态设备的系统和方法
公开(公告)号：US07904667B2
公开(公告)日：2011-03-08
申请号：US11503431
申请日：2006-08-10
申请人： Yunsheng Wang , Casey Springer , Tak Kwong Wong , Bill Beane
发明人： Yunsheng Wang , Casey Springer , Tak Kwong Wong , Bill Beane
IPC分类号： G06F13/20
CPC分类号： G11C7/1075 , G06F13/1663
摘要： A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.
摘要翻译：静态随机存取存储器（SRAM）包括用于监视外部二进制器件状态的输入读寄存器（IRR）和用于控制外部二进制器件状态的输出驱动寄存器（ODR）。 SRAM可以是多端口设备，用于多个处理器或控制器的访问。 IRR的每一位可以反映连接的外部二进制设备的状态。 ODR的每一位可以操纵连接的外部二进制设备的状态，或者可以在不改变状态的情况下读取。存储器件可以包括可设置的控制位和一组受控寄存器位。设置一个或多个控制位可以定义哪些受控寄存器位与IRR相关联并且与ODR相关联。

10. 发明申请

US20100007373A1 IMPEDANCE MATCHING LOGIC 有权
标题翻译：阻抗匹配逻辑
公开(公告)号：US20100007373A1
公开(公告)日：2010-01-14
申请号：US12170012
申请日：2008-07-09
申请人： Tak Kwong Wong
发明人： Tak Kwong Wong
IPC分类号： H03K19/003
CPC分类号： H04L25/0278
摘要： An impedance matching logic generates code values that define pull-up and pull-down transistors to be enabled with output buffers. The output buffers store the code values using a two-stage latch configuration, such that updated code values are always stored within the output buffer, even if the output buffer is driving an output signal when the updated code values are received. The impedance matching logic uses previously determined code values to shorten the time required to calculate updated code values. The impedance matching logic may be operated in response to a clock signal having a frequency lower than the frequency of the output clock signal used to control the output buffers. The impedance matching logic may adjust the code values by certain percentages using a multiplication function, thereby allowing for design fine tuning (e.g., due to layout mismatch).
摘要翻译：阻抗匹配逻辑产生定义上拉和下拉晶体管的代码值，以使能输出缓冲器。输出缓冲器使用两级锁存器配置来存储代码值，使得更新的代码值总是存储在输出缓冲器内，即使当接收到更新的代码值时输出缓冲器正在驱动输出信号。阻抗匹配逻辑使用先前确定的代码值来缩短计算更新代码值所需的时间。阻抗匹配逻辑可以响应于具有低于用于控制输出缓冲器的输出时钟信号的频率的时钟信号来操作。阻抗匹配逻辑可以使用乘法函数来调整代码值一定百分比，从而允许设计精调（例如，由于布局不匹配）。

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