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1. 发明授权

US07222254B2 System and method for over-clocking detection of a processor utilizing a feedback clock rate setting 有权
标题翻译：利用反馈时钟速率设置对处理器进行超频检测的系统和方法
公开(公告)号：US07222254B2
公开(公告)日：2007-05-22
申请号：US10663098
申请日：2003-09-15
申请人： Tsvika Kurts , John W. Horigan
发明人： Tsvika Kurts , John W. Horigan
IPC分类号： G06F5/06 , G06F1/00 , G06F1/04
CPC分类号： H03K5/19 , G06F21/71 , G06F21/725
摘要： A processor provides a configured clock rate setting for use by a peripheral set. The processor receives back from the peripheral set a feedback clock rate setting. The configured clock rate setting and the feedback clock rate setting are compared to detect over-clocking of the processor.
摘要翻译：处理器提供配置的时钟速率设置供外设使用。处理器从外围设备接收反馈时钟速率设置。将配置的时钟速率设置和反馈时钟速率设置进行比较，以检测处理器的超频。

2. 发明授权

US08165160B2 Method and system to validate a write for a device on a serial bus 有权
标题翻译：用于验证串行总线上设备的写入的方法和系统
公开(公告)号：US08165160B2
公开(公告)日：2012-04-24
申请号：US11540837
申请日：2006-09-29
申请人： Robert A. Dunstan , John W. Horigan
发明人： Robert A. Dunstan , John W. Horigan
IPC分类号： H04J3/16
CPC分类号： H04L1/0061 , H04L2001/0094
摘要： A method and system, the method including, in some embodiments, calculating, by a message originator, a first check sum byte, appending the first check sum byte to the message, sending the message from the originator to a client over a single wire serial bus, and determining, by the client, a validity of the message from the originator by comparing the first check sum byte with a second check sum calculated by the client.
摘要翻译：一种方法和系统，所述方法在一些实施例中包括由消息发起者计算第一校验和字节，将第一校验和字节附加到消息，通过单线串行将消息从发起者发送到客户端总线，并且由客户端通过将第一校验和字节与由客户端计算的第二校验和比较来确定来自始发者的消息的有效性。

3. 发明授权

US07694164B2 Operating system-independent method and system of determining CPU utilization 有权
标题翻译：操作系统独立的方法和确定CPU利用率的系统
公开(公告)号：US07694164B2
公开(公告)日：2010-04-06
申请号：US10251202
申请日：2002-09-20
申请人： Avinash P. Chakravarthy , Barnes Cooper , Robert Gough , John W. Horigan
发明人： Avinash P. Chakravarthy , Barnes Cooper , Robert Gough , John W. Horigan
IPC分类号： G06F1/04
CPC分类号： G06F1/3203
摘要： A method and device are provided to monitor clock control signals from a CPU core; and calculate a time period during a sampling interval that the CPU core was used to perform work based on the clock control signals.
摘要翻译：提供了一种方法和装置来监视来自CPU核心的时钟控制信号; 并根据时钟控制信号计算CPU核心被采用执行工作的采样间隔期间的时间段。

4. 发明授权

US07526663B2 Method and apparatus for reducing the power consumed by a computer system 有权
标题翻译：用于减少计算机系统消耗的功率的方法和装置
公开(公告)号：US07526663B2
公开(公告)日：2009-04-28
申请号：US11402527
申请日：2006-04-11
申请人： Don J. Nguyen , Pochang Hsu , Robert T. Jackson , John W. Horigan
发明人： Don J. Nguyen , Pochang Hsu , Robert T. Jackson , John W. Horigan
IPC分类号： G06F1/26
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172 , Y02D50/20
摘要： A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.
摘要翻译：具有能够处于唤醒或休眠状态的一个或多个组件的计算机系统包括功率管理器和电压调节器。功率管理器可以产生指示组件的功率状态的功率状态信号，并且该信号可以被提供给电压调节器。电压调节器可以向组件供电。功率的目标电压电平可以取决于电力的当前电平和功率状态信号。

5. 发明授权

US07191349B2 Mechanism for processor power state aware distribution of lowest priority interrupt 有权
标题翻译：处理器电源状态识别分配最低优先级中断的机制
公开(公告)号：US07191349B2
公开(公告)日：2007-03-13
申请号：US10330622
申请日：2002-12-26
申请人： Shivnandan D. Kaushik , John W. Horigan , Alon Naveh , James B. Crossland
发明人： Shivnandan D. Kaushik , John W. Horigan , Alon Naveh , James B. Crossland
IPC分类号： G06F1/00 , G06F1/30 , G06F1/32
CPC分类号： G06F9/3851 , G06F1/3203 , G06F1/3243 , G06F1/329 , G06F9/4812 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
摘要： A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.
摘要翻译：一种用于处理器功率状态识别分配最低优先级中断的机制的方法。一个实施例的方法包括从第一组件接收第一功率状态信息和从第二组件接收第二功率状态信息。还接收来自第一分量的第一任务优先级信息和来自第二分量的第二任务优先级。接收来自第一设备的用于维修的中断请求。评估第一和第二组件的功率状态和任务优先级信息，以确定哪个组件应该服务于中断请求。选择第一组件或第二组件作为目的组件，以基于功率状态和任务优先级信息来服务中断请求。中断请求被传送到目标组件。

6. 发明授权

US06976181B2 Method and apparatus for enabling a low power mode for a processor 有权
标题翻译：用于为处理器启用低功率模式的方法和装置
公开(公告)号：US06976181B2
公开(公告)日：2005-12-13
申请号：US10027939
申请日：2001-12-20
申请人： Xia Dai , John W. Horigan , Millind Mittal , Leslie E. Cline
发明人： Xia Dai , John W. Horigan , Millind Mittal , Leslie E. Cline
IPC分类号： G06F1/32 , G06F12/08 , G06F1/26
CPC分类号： G06F1/3203 , G06F12/0891
摘要： In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicate the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.
摘要翻译：根据本发明的实施例，启动触发事件以将处理器置于低功率状态。根据电源状态信号，处理器可能进入或不进入低功率状态时刷新高速缓存。功率状态信号可以指示与将处理器置于低功率状态相关联的功率降低的相对优先级，而不首先冲洗高速缓存，而与高功率状态中的电压降低相关联的高速缓存中的软错误率的增加。

7. 发明授权

US06384651B1 Method of generating a signal with controlled duty-cycle and pseudo-random spectrum 有权
标题翻译：产生具有受控占空比和伪随机频谱的信号的方法
公开(公告)号：US06384651B1
公开(公告)日：2002-05-07
申请号：US09536906
申请日：2000-03-28
申请人： John W. Horigan
发明人： John W. Horigan
IPC分类号： H03K3017
CPC分类号： G06F1/3237 , G06F1/04 , G06F1/3203 , Y02D10/128
摘要： A method is disclosed including generating a digital control signal having a duty cycle which varies randomly or pseudo-randomly between a number of cycles, and is substantially fixed when averaged over the cycles. A target signal such as a digital clock signal may be passed selectively, in accordance with the control signal. A particular application of the method is power management in computers and other electronic systems that feature high performance processor and memory configurations that involve synchronous accesses of the memory by the processor.
摘要翻译：公开了一种方法，其包括产生具有在多个周期之间随机或伪随机变化的占空比的数字控制信号，并且在周期上平均时基本上是固定的。可以根据控制信号选择性地传送诸如数字时钟信号的目标信号。该方法的特定应用是计算机和其他电子系统中的电源管理，其特征在于高性能处理器和存储器配置，其涉及处理器对存储器的同步访问。

8. 发明授权

US06961864B2 Method and apparatus for terminating clock signals upon disconnection of clock trace from ground 失效
标题翻译：断开时钟迹线与地面断开时钟信号的方法和装置
公开(公告)号：US06961864B2
公开(公告)日：2005-11-01
申请号：US10150317
申请日：2002-05-16
申请人： John W. Horigan
发明人： John W. Horigan
IPC分类号： G06F1/10 , G06F1/32 , G06F1/04
CPC分类号： H03K5/151 , G06F1/10 , G06F1/3203 , H03K19/1732
摘要： According to one embodiment, a computer system is disclosed. The computer system includes a first clock receiver, one or more clock traces coupled to the clock generator, and clock generator coupled to the one or more clock traces. The clock generator gates clock signals to the first clock receiver in response to detecting that the clock traces have been disconnected from electrical ground.
摘要翻译：根据一个实施例，公开了一种计算机系统。计算机系统包括第一时钟接收器，耦合到时钟发生器的一个或多个时钟迹线以及耦合到一个或多个时钟迹线的时钟发生器。响应于检测到时钟迹线已经从电气接地断开，时钟发生器将时钟信号施加到第一时钟接收器。

9. 发明授权

US06566848B2 Auto-calibrating voltage regulator with dynamic set-point capability 有权
标题翻译：具有动态设定点功能的自动校准电压调节器
公开(公告)号：US06566848B2
公开(公告)日：2003-05-20
申请号：US09749090
申请日：2000-12-26
申请人： John W. Horigan , Daniel F. Gilbride , Don J. Nguyen
发明人： John W. Horigan , Daniel F. Gilbride , Don J. Nguyen
IPC分类号： G05F140
CPC分类号： G05F1/56
摘要： A voltage regulator is described which uses external resistors to set a load line and offset. During initial operation and also during normal operation the load line and offset are reset by placing, for instance, the microprocessor in a high active state, low active state and in a sleep mode. By dynamically changing the load line and offset voltage, minimum current is drawn thus extending battery life.
摘要翻译：描述了一种使用外部电阻来设置负载线和偏置的稳压器。在初始操作期间，并且在正常操作期间，通过将例如微处理器置于高活动状态，低活动状态和睡眠模式来重置负载线和偏移。通过动态改变负载线和失调电压，可以减少最小电流从而延长电池寿命。

10. 发明授权

US6157233A Always-deterministic phase-locked loop 有权
标题翻译：总是确定性的锁相环
公开(公告)号：US6157233A
公开(公告)日：2000-12-05
申请号：US212541
申请日：1998-12-16
申请人： John W. Horigan , Rajendra M. Abhyankar
发明人： John W. Horigan , Rajendra M. Abhyankar
IPC分类号： G06F1/08 , G06F1/12 , H03L7/08 , H03L7/18 , H03L7/00
CPC分类号： H03L7/08 , G06F1/08 , G06F1/12 , H03L7/18
摘要： In some embodiments, the invention includes a system having a normal operating mode and a suspend mode. The system includes event recognition circuitry to provide an event status signal. The system also includes clock generating circuitry with selective stretching capability to generate an internal clock signal and to receive the event status signal, and wherein when the event status signal has a first logic state, the clock generating circuitry stretches the internal clock signal by a number of phases per cycle of a bus clock signal wherein an alignment relationship between the internal clock signal and the bus clock signal is immediately deterministic in transitions between the suspend mode and the normal operating mode.
摘要翻译：在一些实施例中，本发明包括具有正常操作模式和挂起模式的系统。该系统包括提供事件状态信号的事件识别电路。该系统还包括具有选择性拉伸能力的时钟产生电路以产生内部时钟信号并接收事件状态信号，并且其中当事件状态信号具有第一逻辑状态时，时钟产生电路将内部时钟信号延伸一个数字每个周期的每个周期的相位，其中在暂停模式和正常操作模式之间的转换中，内部时钟信号和总线时钟信号之间的对准关系是立即确定的。

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