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    • 6. 发明授权
    • Voltage generating circuit for semiconductor memory sense amplifier
    • 半导体存储器读出放大器的电压产生电路
    • US06169698A
    • 2001-01-02
    • US09189076
    • 1998-11-09
    • Shunichi SukegawaShinji BesshoMasayuki HiraYasushi TakahashiTsutomu TakahashiKoji Arai
    • Shunichi SukegawaShinji BesshoMasayuki HiraYasushi TakahashiTsutomu TakahashiKoji Arai
    • G11C700
    • G11C5/063G11C5/143G11C5/147G11C7/06
    • Drop in the power supply level right after change can be suppressed greatly when changing the power to the internal power supply voltage from the external power supply voltage of an overdrive system. Voltage generating circuit VG0 is connected to the VDL line which raises the VDL line to a voltage higher than VDL beforehand prior to changing to internal power supply voltage VDL from external power supply voltage VDD, and restores the VDL line voltage which drops after the change to VDL. More specifically, there are detecting circuit part 40 which detects the VDL line potential, first switching element M1 connected between the VDL line and the VDD line and which operates according to the detected result of detecting circuit part 40, and second switching element M2 connected between common voltage VSS and connection node ND1 between first switching element M1 and detecting circuit part 40, which changes the potential of connection node ND1 by conducting according to input preliminary voltage step up signal MVDL, and by it conducts first switching element M1 for a fixed time.
    • 在从过驱动系统的外部电源电压改变内部电源电压的电源时,可以大幅度地抑制变更后的电源电平下降。 在从外部电源电压VDD变为内部电源电压VDL之前,将电压生成电路VG0与VDL线连接,将VDL线预先升压至高于VDL的电压,并且将变更后降低的VDL线电压恢复为 VDL。 更具体地,存在检测VDL线电位的检测电路部40,连接在VDL线与VDD线之间的第一开关元件M1,其根据检测电路部40的检测结果进行动作,第二开关元件M2连接在 第一开关元件M1和检测电路部分40之间的公共电压VSS和连接节点ND1,其通过根据输入的初步升压信号MVDL进行导通来改变连接节点ND1的电位,并且通过其将第一开关元件M1导通固定时间 。
    • 7. 发明授权
    • Overall VPP well form
    • 总体VPP表格
    • US6002162A
    • 1999-12-14
    • US90721
    • 1998-06-04
    • Yasushi TakahashiTsutomu TakahashiKoji AraiShinji BesshoShunichi SukegawaMasayuki Hira
    • Yasushi TakahashiTsutomu TakahashiKoji AraiShinji BesshoShunichi SukegawaMasayuki Hira
    • H01L21/8242G11C11/407G11C11/4074G11C11/408G11C11/409H01L27/108H01L29/72
    • H01L27/10897G11C11/4074
    • Realizing a reduction of the layout surface area by rendering unnecessary the region used for well isolation. In this DRAM, a triple well construction is used, and all of the regions for the unit memory cell array MA, the word line driver bank WDB, the sense amplifier bank SAB, and the cross area CR are surrounded by a lower layer N-type deep (deep layer) well 12. A back bias VPP corresponding to the power supply voltage of the word line driver is applied to the N well 14, and a back bias VBB corresponding to the characteristics of the memory cell are applied to the P well 16. In the N well 14, in regard to the P-type MOS transistors of the sense amplifier that undergo the substrate bias effect due to the back bias VPP, the threshold voltage is set to a low value so as to cancel that bias effect. Also, in the P well 16, in regard to the N-type MOS transistors of the sense amplifiers that undergo the substrate bias effect due to the back bias VBB, the threshold voltage is designed to a low value so as to cancel that bias effect.
    • 通过使用于隔离的区域不必要地实现布局表面积的减小。 在该DRAM中,使用三阱结构,并且用于单位存储单元阵列MA,字线驱动器组WDB,读出放大器组SAB和交叉区域CR的所有区域被下层N- 类型深(深层)阱12.对应于字线驱动器的电源电压的背偏压VPP被施加到N阱14,并且对应于存储器单元的特性的反偏压VBB被施加到P 在N阱14中,关于由于反偏压VPP而经历衬底偏置效应的读出放大器的P型MOS晶体管,阈值电压被设置为低值,以抵消该偏置 影响。 此外,在P阱16中,关于由于背偏压VBB而经历衬底偏置效应的读出放大器的N型MOS晶体管,阈值电压被设计为低值,以抵消该偏置效应 。
    • 8. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US5970010A
    • 1999-10-19
    • US116915
    • 1998-07-17
    • Masayuki HiraShunichi SukegawaShinji BesshoYasushi TakahashiKoji AraiTsutomu TakahashiTsugio Takahashi
    • Masayuki HiraShunichi SukegawaShinji BesshoYasushi TakahashiKoji AraiTsutomu TakahashiTsugio Takahashi
    • G11C11/409G11C7/06G11C11/401G11C11/4091H01L21/8242H01L27/108G11C7/00
    • G11C7/065G11C11/4091
    • Controlling the timing for the overdrive of the sense amplifiers in response to the wiring length between the sense amplifiers and the power supply voltage supply nodes, and designing a reduction of the power consumption by preventing excessive overdrive of the bit lines.The supply timing for the power supply voltage to each sense amplifier bank is controlled according to the wiring length between the supply nodes CT0, CT1, CT2 for the power supply used for the driving of the sense amplifiers and each sense amplifier bank SB0 to SB16, and since the supply time for the overdrive voltage to the sense amplifier bank SB0 at the near end is set short and the supply time for the overdrive voltage is set successively longer as it goes towards the far end, the sensing delay that originates in the voltage drop that is generated in the wiring between the supply nodes and the sense amplifier banks is compensated for, uniformity of the overdrive for the bit lines at both the far and near ends can be achieved, the excessive overdrive at the sense amplifier bank (memory cell mat) at the near end can be avoided, and by extension, a reduction of the power consumption can be realized.
    • 响应于读出放大器和电源电压节点之间的布线长度来控制感测放大器的过驱动的定时,以及通过防止位线的过度过载来设计功耗的降低。 根据用于驱动读出放大器和每个读出放大器组SB0至SB16的电源的供电节点CT0,CT1,CT2之间的布线长度,控制每个感测放大器组的电源电压的供应定时, 并且由于将近端的读出放大器组SB0的过驱动电压的供给时间设定得较短,并且对于过驱动电压的供给时间随着朝向远端而连续设定,所以产生于电压的感测延迟 在供电节点和感测放大器组之间的布线中产生的下降被补偿,可以实现在远端和近端的位线的过驱动的均匀性,在感测放大器组(存储单元)处的过度过驱动 垫)可以避免,并且通过扩展,可以实现功率消耗的降低。
    • 9. 发明授权
    • Semiconductor memory device having a back gate voltage controlled delay
circuit
    • 具有背栅电压控制延迟电路的半导体存储器件
    • US6034920A
    • 2000-03-07
    • US198816
    • 1998-11-24
    • Shunichi SukegawaShinji BesshoTadashi TachibanaHiroyuki Yoshida
    • Shunichi SukegawaShinji BesshoTadashi TachibanaHiroyuki Yoshida
    • G11C7/06G11C8/18G11C8/00
    • G11C8/18G11C7/06
    • A semiconductor memory device has an address buffer (200, 230). A pre-decoder circuit (202, 232) receives the output of the address buffer (200, 230), and a memory array (212) receives the output of the pre-decoder circuit. A main amplifier (216, 248) in turn receives the output of the memory array (212, 244). An address transition detector (ATD) pulse generator circuit (204, 234) also receives the output of the address buffer (200, 230), and a pulse delay circuit (208, 240) receives the output of the address transition detector pulse generator circuit (204, 234). The pulse delay circuit (208, 240) also provides a main amplifier signal to the main amplifier (216, 248). The memory device further includes a voltage generator (206, 236) that generates a back gate voltage which is provided as a low voltage supply (V.sub.BB) for the address transition detector (ATD) pulse generator circuit (204, 234) and the pulse delay circuit (208, 240). The address transition detector (ATD) pulse generator (204, 234) and the pulse delay circuit (208, 240) have a delay that is controlled by the back gate voltage (V.sub.BB) and has a reduced dependency on a high voltage supply (V.sub.DD) of the memory device.
    • 半导体存储器件具有地址缓冲器(200,230)。 预解码器电路(202,232)接收地址缓冲器(200,230)的输出,存储器阵列(212)接收预解码器电路的输出。 主放大器(216,248)又接收存储器阵列(212,244)的输出。 地址转换检测器(ATD)脉冲发生器电路(204,234)还接收地址缓冲器(200,230)的输出,并且脉冲延迟电路(208,240)接收地址转换检测器脉冲发生器电路的输出 (204,234)。 脉冲延迟电路(208,240)还向主放大器(216,248)提供主放大器信号。 存储装置还包括产生背栅电压的电压发生器(206,236),该栅极电压作为用于地址转换检测器(ATD)脉冲发生器电路(204,234)的低电压电源(VBB)和脉冲延迟 电路(208,240)。 地址转换检测器(ATD)脉冲发生器(204,234)和脉冲延迟电路(208,240)具有由背栅极电压(VBB)控制的延迟,并且对高电压源(VDD)的依赖性降低 )的存储器件。