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1. 发明授权

US06683352B2 Semiconductor device structure 有权
标题翻译：半导体器件结构
公开(公告)号：US06683352B2
公开(公告)日：2004-01-27
申请号：US10078314
申请日：2002-02-15
申请人： Tsung-Hsuan Hsieh , Yao-Wen Chang , Tao-Cheng Lu
发明人： Tsung-Hsuan Hsieh , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L2976
CPC分类号： H01L21/823425 , H01L21/823443 , H01L29/4238 , H01L29/665
摘要： A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is disposed within the semiconductor substrate, wherein the drain region is surrounded by the p-shape gate. A source region is disposed within the semiconductor substrate, wherein the source region surrounds the p-shape gate. A silicide structure is disposed on the source/drain regions and the p-shape gate.
摘要翻译：公开了一种金属氧化物半导体场效应晶体管结构。 p型栅极，设置在半导体衬底上。栅极电介质层设置在p型栅极和半导体衬底之间。漏极区域设置在半导体衬底内，其中漏极区域被p型栅极包围。源极区域设置在半导体衬底内，其中源极区域围绕p形栅极。在源极/漏极区域和p形栅极上设置硅化物结构。

2. 发明授权

US06549029B1 Circuit and method for measuring capacitance 有权
标题翻译：用于测量电容的电路和方法
公开(公告)号：US06549029B1
公开(公告)日：2003-04-15
申请号：US09990261
申请日：2001-11-20
申请人： Tsung-Hsuan Hsieh , Yao-Wen Chang , Tao-Cheng Lu
发明人： Tsung-Hsuan Hsieh , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： G01R3126
CPC分类号： G01R27/2605
摘要： A circuit structure for measuring a capacitive load. The capacitive load is coupled between a first and a second nodes, and drains of a first PMOS and a first NMOS transistors are coupled to the first node, and drains of a second PMOS and a second NMOS transistors are coupled to the second node, and a pad is coupled to the second node. First, sources of the first and the second PMOS transistors and sources of the first and the second NMOS transistors are biased at a power source and a ground respectively. A non-synchronized voltage is applied to gates of the first and the second PMOS transistors and to gates of the first and the second NMOS transistors simultaneously. By grounding and floating the pad, a current flowing through the capacitive load is obtained to calculate the capacitance.
摘要翻译：用于测量电容性负载的电路结构。电容性负载耦合在第一和第二节点之间，并且第一PMOS和第一NMOS晶体管的漏极耦合到第一节点，并且第二PMOS和第二NMOS晶体管的漏极耦合到第二节点，并且垫连接到第二节点。首先，第一和第二PMOS晶体管的源极和第一和第二NMOS晶体管的源极分别偏置在电源和地。非同步电压同时施加到第一和第二PMOS晶体管的栅极和第一和第二NMOS晶体管的栅极。通过接地和浮动焊盘，获得流过电容性负载的电流来计算电容。

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