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1. 发明授权

US08334525B2 Nonvolatile semiconductor memory device including a variable resistance layer including carbon 有权
标题翻译：包括包含碳的可变电阻层的非易失性半导体存储器件
公开(公告)号：US08334525B2
公开(公告)日：2012-12-18
申请号：US12825975
申请日：2010-06-29
申请人： Tsukasa Nakai , Hiroyuki Fukumizu , Yasuhiro Nojiri , Motoya Kishida , Kazuyuki Yahiro , Yasuhiro Satoh
发明人： Tsukasa Nakai , Hiroyuki Fukumizu , Yasuhiro Nojiri , Motoya Kishida , Kazuyuki Yahiro , Yasuhiro Satoh
IPC分类号： H01L29/02
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2481 , H01L45/1233 , H01L45/126 , H01L45/14 , H01L45/1616 , H01L45/1625
摘要： According to one embodiment, a variable resistance layer includes a mixture of a first compound and a second compound. The first compound includes carbon (C) as well as at least one element selected from a group of elements G1. The group of elements G1 consists of hydrogen (H), boron (B), nitrogen (N), silicon (Si), and titanium (Ti). The second compound includes at least one compound selected from a group of compounds G2. The group of compounds G2 consists of silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (Si3N4), carbon nitride (C3N4), boron nitride (BN), aluminum nitride (AlN), aluminum oxide (Al2O3), and silicon carbide (SiC). Concentration of the first compound in the variable resistance layer is not less than 30 volume percent, and not more than 70 volume percent.
摘要翻译：根据一个实施方案，可变电阻层包括第一化合物和第二化合物的混合物。第一化合物包括碳（C）以及选自元素组G1的至少一种元素。元素组G1由氢（H），硼（B），氮（N），硅（Si）和钛（Ti）组成。第二化合物包括选自化合物G2的至少一种化合物。化合物组G2由氧化硅（SiO 2），氮氧化硅（SiON），氮化硅（Si 3 N 4），碳氮化物（C 3 N 4），氮化硼（BN），氮化铝（AlN），氧化铝（Al 2 O 3）和碳化硅（SiC）。可变电阻层中第一化合物的浓度不小于30体积％，不大于70体积％。

2. 发明授权

US08378331B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US08378331B2
公开(公告)日：2013-02-19
申请号：US12707136
申请日：2010-02-17
申请人： Yasuhiro Satoh , Tsukasa Nakai , Kazuhiko Yamamoto , Motoya Kishida , Hiroyuki Fukumizu , Yasuhiro Nojiri
发明人： Yasuhiro Satoh , Tsukasa Nakai , Kazuhiko Yamamoto , Motoya Kishida , Hiroyuki Fukumizu , Yasuhiro Nojiri
IPC分类号： H01L29/02
CPC分类号： H01L45/1233 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/149 , H01L45/1641
摘要： This nonvolatile semiconductor memory device comprises a memory cell array including memory cells arranged therein. Each of the memory cells is located at respective intersections between first wirings and second wirings and includes a variable resistance element. The variable resistance element comprises a thin film including carbon (C). The thin film includes a side surface along a direction of a current flowing in the memory cell. The side surface includes carbon nitride (CNx).
摘要翻译：该非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括布置在其中的存储单元。每个存储单元位于第一布线和第二布线之间的相应交点处，并且包括可变电阻元件。可变电阻元件包括包含碳（C）的薄膜。薄膜包括沿着在存储单元中流动的电流的方向的侧表面。侧表面包括碳氮化物（CNx）。

3. 发明申请

US20100237319A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100237319A1
公开(公告)日：2010-09-23
申请号：US12707136
申请日：2010-02-17
申请人： Yasuhiro SATOH , Tsukasa Nakai , Kazuhiko Yamamoto , Motoya Kishida , Hiroyuki Fukumizu , Yasuhiro Nojiri
发明人： Yasuhiro SATOH , Tsukasa Nakai , Kazuhiko Yamamoto , Motoya Kishida , Hiroyuki Fukumizu , Yasuhiro Nojiri
IPC分类号： H01L45/00
CPC分类号： H01L45/1233 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/149 , H01L45/1641
摘要： This nonvolatile semiconductor memory device comprises a memory cell array including memory cells arranged therein. Each of the memory cells is located at respective intersections between first wirings and second wirings and includes a variable resistance element. The variable resistance element comprises a thin film including carbon (C). The thin film includes a side surface along a direction of a current flowing in the memory cell. The side surface includes carbon nitride (CNx).
摘要翻译：该非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括布置在其中的存储单元。每个存储单元位于第一布线和第二布线之间的相应交点处，并且包括可变电阻元件。可变电阻元件包括包含碳（C）的薄膜。薄膜包括沿着在存储单元中流动的电流的方向的侧表面。侧表面包括碳氮化物（CNx）。

4. 发明授权

US08339834B2 Non-volatile semiconductor memory device including a variable resistance element 有权
标题翻译：包括可变电阻元件的非易失性半导体存储器件
公开(公告)号：US08339834B2
公开(公告)日：2012-12-25
申请号：US12882822
申请日：2010-09-15
申请人： Tsukasa Nakai , Yasuhiro Nojiri , Shuichi Kuboi , Motoya Kishida , Akiko Nomachi , Masanobu Baba , Hiroyuki Fukumizu
发明人： Tsukasa Nakai , Yasuhiro Nojiri , Shuichi Kuboi , Motoya Kishida , Akiko Nomachi , Masanobu Baba , Hiroyuki Fukumizu
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： G11C14/00 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1616
摘要： According to one embodiment, a non-volatile semiconductor memory device includes: a first line; a second line intersecting with the first line; and a memory cell arranged at a position where the second line intersects with the first line, wherein, the memory cell includes: a variable resistance element; and a negative resistance element connected in series to the variable resistance element.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括：第一线; 与第一行相交的第二行; 以及布置在所述第二线与所述第一线相交的位置的存储单元，其中，所述存储单元包括：可变电阻元件; 以及与可变电阻元件串联连接的负电阻元件。

5. 发明申请

US20110205781A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110205781A1
公开(公告)日：2011-08-25
申请号：US12882822
申请日：2010-09-15
申请人： Tsukasa Nakai , Yasuhiro Nojiri , Shuichi Kuboi , Motoya Kishida , Akiko Nomachi , Masanobu Baba , Hiroyuki Fukumizu
发明人： Tsukasa Nakai , Yasuhiro Nojiri , Shuichi Kuboi , Motoya Kishida , Akiko Nomachi , Masanobu Baba , Hiroyuki Fukumizu
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： G11C14/00 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1616
摘要： According to one embodiment, a non-volatile semiconductor memory device includes: a first line; a second line intersecting with the first line; and a memory cell arranged at a position where the second line intersects with the first line, wherein, the memory cell includes: a variable resistance element; and a negative resistance element connected in series to the variable resistance element.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括：第一线; 与第一行相交的第二行; 以及布置在所述第二线与所述第一线相交的位置的存储单元，其中，所述存储单元包括：可变电阻元件; 以及与可变电阻元件串联连接的负电阻元件。

6. 发明申请

US20060097303A1 Semiconductor device and its manufacturing method 审中-公开
公开(公告)号：US20060097303A1
公开(公告)日：2006-05-11
申请号：US11312388
申请日：2005-12-21
申请人： Takeo Furuhata , Ichiro Mizushima , Akiko Sekihara , Motoya Kishida , Tsubasa Harada , Takashi Nakao
发明人： Takeo Furuhata , Ichiro Mizushima , Akiko Sekihara , Motoya Kishida , Tsubasa Harada , Takashi Nakao
IPC分类号： H01L29/94
CPC分类号： H01L21/76847 , H01L21/76864 , H01L27/10867 , H01L29/945
摘要： A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.

7. 发明授权

US07235490B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07235490B2
公开(公告)日：2007-06-26
申请号：US10788216
申请日：2004-02-27
申请人： Yasuhiko Sato , Seiji Nakagawa , Jun Idebuchi , Motoya Kishida , Shuichi Taniguchi , Tsuyoshi Shibata
发明人： Yasuhiko Sato , Seiji Nakagawa , Jun Idebuchi , Motoya Kishida , Shuichi Taniguchi , Tsuyoshi Shibata
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , G03F7/09 , H01L21/0332
摘要： A method of manufacturing a semiconductor device comprises preparing a working film to be processed, forming an adhesion improving region on the working film for increasing an adhesion between the working film and a mask material containing carbon, forming the mask material on the working film, forming a resist pattern on the mask material, the mask material having a higher etching resistance for the working film than the resist pattern, transferring the pattern of the resist pattern onto the mask material, and etching the working film by using the mask material as a mask.
摘要翻译：一种制造半导体器件的方法包括：制备待加工的工作薄膜，在工作薄膜上形成粘合改善区域，以增加工作薄膜和含有碳的掩模材料之间的粘附力，在工作薄膜上形成掩模材料，形成在掩模材料上的抗蚀剂图案，掩模材料对抗蚀剂图案具有比工作膜更高的耐蚀刻性，将抗蚀剂图案的图案转印到掩模材料上，并且通过使用掩模材料作为掩模来蚀刻工作膜。

8. 发明授权

US07045417B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07045417B2
公开(公告)日：2006-05-16
申请号：US11061531
申请日：2005-02-22
申请人： Yoshio Kasai , Miki Kawase , Takashi Suzuki , Motoya Kishida
发明人： Yoshio Kasai , Miki Kawase , Takashi Suzuki , Motoya Kishida
IPC分类号： H01L21/8242
CPC分类号： H01L27/10829 , H01L27/10867
摘要： A method of manufacturing a semiconductor device, which comprises forming a first semiconductor film on a surface of a semiconductor substrate, adsorbing a first impurity on a surface of the first semiconductor film, adsorbing a second impurity on the surface of the first semiconductor film, forming a second semiconductor film on the surface of the first semiconductor film, and solid-phase-diffusing the first impurity and the second impurity into a region of the semiconductor substrate which is located adjacent to the first and second semiconductor films to thereby form a first diffusion region containing the first impurity and a second diffusion region containing the second impurity, a concentration of the first impurity in the first diffusion region being higher than that of the second impurity in the second diffusion region, and the first diffusion region having the bottom thereof covered by the second diffusion region.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底的表面上形成第一半导体膜，在第一半导体膜的表面上吸附第一杂质，在第一半导体膜的表面上吸附第二杂质，形成在所述第一半导体膜的表面上的第二半导体膜，并且将所述第一杂质和所述第二杂质固相扩散到所述半导体衬底的与所述第一和第二半导体膜相邻的区域中，从而形成第一扩散含有第一杂质的区域和含有第二杂质的第二扩散区域，第一扩散区域中的第一杂质的浓度高于第二扩散区域中的第二杂质浓度，第一扩散区域的底部被覆盖通过第二扩散区域。

9. 发明授权

US07995374B2 Semiconductor memory device, method of manufacturing the same, and method of screening the same 有权
标题翻译：半导体存储器件及其制造方法及其筛选方法
公开(公告)号：US07995374B2
公开(公告)日：2011-08-09
申请号：US12618122
申请日：2009-11-13
申请人： Masanori Komura , Mitsuru Sato , Kenichi Murooka , Motoya Kishida
发明人： Masanori Komura , Mitsuru Sato , Kenichi Murooka , Motoya Kishida
IPC分类号： G11C11/00 , G11C11/36 , G11C17/00 , G11C29/00
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/004 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1625 , H01L45/1675
摘要： A memory cell comprises a variable resistance film; a first conductive film having one surface contacted with one surface of the variable resistance film; and a second conductive film having one surface contacted with another surface of the variable resistance film. A width of the first conductive film or the second conductive film in a direction orthogonal to a direction that a current flows in the first conductive film or the second conductive film is smaller than a width of the variable resistance film in a direction orthogonal to a direction that a current flows in the variable resistance film. The width of the first conductive film and the second conductive film is smaller than a width of the first line and the second line in a direction orthogonal to a direction that a current flows in the first line and the second line.
摘要翻译：存储单元包括可变电阻膜; 具有与所述可变电阻膜的一个表面接触的一个表面的第一导电膜; 以及具有与可变电阻膜的另一表面接触的一个表面的第二导电膜。第一导电膜或第二导电膜在与第一导电膜或第二导电膜中的电流方向正交的方向上的宽度小于在与方向正交的方向上的可变电阻膜的宽度电流在可变电阻膜中流动。第一导电膜和第二导电膜的宽度小于与第一线和第二线中的电流方向正交的方向上的第一线和第二线的宽度。

10. 发明授权

US07126178B2 Semiconductor device and its manufacturing method 失效
公开(公告)号：US07126178B2
公开(公告)日：2006-10-24
申请号：US11068848
申请日：2005-03-02
申请人： Takeo Furuhata , Ichiro Mizushima , Akiko Sekihara , Motoya Kishida , Tsubasa Harada , Takashi Nakao
发明人： Takeo Furuhata , Ichiro Mizushima , Akiko Sekihara , Motoya Kishida , Tsubasa Harada , Takashi Nakao
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L21/76847 , H01L21/76864 , H01L27/10867 , H01L29/945
摘要： A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.

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