专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07844921B2 Interface apparatus and interface method 有权
标题翻译：接口设备和接口方法
公开(公告)号：US07844921B2
公开(公告)日：2010-11-30
申请号：US11757159
申请日：2007-06-01
申请人： Tsukasa Ike , Yasuhiro Taniguchi , Ryuzo Okada , Nobuhisa Kishikawa , Kentaro Yokoi , Mayumi Yuasa , Bjorn Stenger
发明人： Tsukasa Ike , Yasuhiro Taniguchi , Ryuzo Okada , Nobuhisa Kishikawa , Kentaro Yokoi , Mayumi Yuasa , Bjorn Stenger
IPC分类号： G06F3/33 , G09G5/36
CPC分类号： G06F3/017 , G06K9/00355 , G06K9/4614
摘要： An apparatus for a user to interface with a control object apparatus by a posture or a motion of the user's physical part. An image input unit inputs an image including the user's physical part. A gesture recognition unit recognizes the posture or the motion of the user's physical part from the image. A control unit controls the control object apparatus based on an indication corresponding to the posture or the motion. A gesture information display unit displays an exemplary image of the posture or the motion recognized for the user's reference to indicate the control object apparatus.
摘要翻译：用于用户通过用户物理部分的姿势或运动与控制对象装置进行接口的装置。图像输入单元输入包括用户物理部分的图像。手势识别单元从图像识别用户物理部分的姿势或运动。控制单元基于与姿势或运动对应的指示来控制控制对象装置。手势信息显示单元显示为了用户的参考识别的姿势或运动的示例性图像，以指示控制对象装置。

2. 发明申请

US20080052643A1 INTERFACE APPARATUS AND INTERFACE METHOD 有权
标题翻译：界面装置和界面方法
公开(公告)号：US20080052643A1
公开(公告)日：2008-02-28
申请号：US11757159
申请日：2007-06-01
申请人： Tsukasa IKE , Yasuhiro Taniguchi , Ryuzo Okada , Nobuhisa Kishikawa , Kentaro Yokoi , Mayumi Yuasa , Bjorn Stenger
发明人： Tsukasa IKE , Yasuhiro Taniguchi , Ryuzo Okada , Nobuhisa Kishikawa , Kentaro Yokoi , Mayumi Yuasa , Bjorn Stenger
IPC分类号： G06F3/033
CPC分类号： G06F3/017 , G06K9/00355 , G06K9/4614
摘要： An apparatus for a user to interface with a control object apparatus by a posture or a motion of the user's physical part. An image input unit inputs an image including the user's physical part. A gesture recognition unit recognizes the posture or the motion of the user's physical part from the image. A control unit controls the control object apparatus based on an indication corresponding to the posture or the motion. A gesture information display unit displays an exemplary image of the posture or the motion recognized for the user's reference to indicate the control object apparatus.
摘要翻译：用于用户通过用户物理部分的姿势或运动与控制对象装置进行接口的装置。图像输入单元输入包括用户物理部分的图像。手势识别单元从图像识别用户物理部分的姿势或运动。控制单元基于与姿势或运动对应的指示来控制控制对象装置。手势信息显示单元显示为了用户的参考识别的姿势或运动的示例性图像，以指示控制对象装置。

3. 发明申请

US20080141181A1 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM 审中-公开
标题翻译：信息处理设备，信息处理方法和程序
公开(公告)号：US20080141181A1
公开(公告)日：2008-06-12
申请号：US11951760
申请日：2007-12-06
申请人： SATORU ISHIGAKI , Tsukasa Ike , Yasuhiro Taniguchi , Hisashi Kazama
发明人： SATORU ISHIGAKI , Tsukasa Ike , Yasuhiro Taniguchi , Hisashi Kazama
IPC分类号： G06F3/048
CPC分类号： G06F3/017 , G06F3/011 , G06F3/0482 , G06F3/04847
摘要： According to one embodiment, there is provided an information processing apparatus. A hand-shape database stores first data representing a first hand shape and second data representing a second hand shape. A hand-shape recognition unit determines whether a received image includes one of the first and second hand shapes. The hand-shape recognition unit outputs first predetermined information when the image includes the first hand shape, and outputs second predetermined information when the image includes the second hand shape. When the first predetermined information is received, a gesture interpretation unit displays on a display a user interface including display items each associated with an executable function, and selects one of the display items in accordance with the position information. When the second predetermined information is received in a state where one of the display items is selected, the gesture interpretation unit executes the function associated with the selected display item.
摘要翻译：根据一个实施例，提供了一种信息处理装置。手形数据库存储表示第一手形状的第一数据和表示秒针形状的第二数据。手形识别单元确定接收到的图像是否包括第一和第二手形状之一。当图像包括第一手形状时，手形识别单元输出第一预定信息，并且当图像包括秒针形状时输出第二预定信息。当接收到第一预定信息时，手势解释单元在显示器上显示包括与可执行功能相关联的显示项目的用户界面，并且根据位置信息选择一个显示项目。当在选择一个显示项目的状态下接收到第二预定信息时，手势解释单元执行与所选择的显示项目相关联的功能。

4. 发明授权

US08351254B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08351254B2
公开(公告)日：2013-01-08
申请号：US12818248
申请日：2010-06-18
申请人： Yasuhiro Taniguchi
发明人： Yasuhiro Taniguchi
IPC分类号： G11C11/34
CPC分类号： H01L29/788 , G11C16/0433 , G11C2216/10 , H01L27/11521 , H01L27/11558
摘要： The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge storage portion having a floating gate electrode and a storage portion p-well. The floating gate electrode is so placed that it overlaps with part of the first n-well and the second n-well. The storage portion p-well is placed in the first n-well so that it partly overlaps with the floating gate electrode. In this nonvolatile memory cell, memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well.
摘要翻译：提高了包括非易失性存储器的半导体器件的性能。布置在硅衬底上的每个非易失性存储单元包括：第一n阱; 在不同于其位置的地方形成的第二个n阱; 形成在第一n阱中的选择晶体管; 以及具有浮置栅极电极和存储部分p阱的电荷存储部分。浮栅电极被放置成使其与第一n阱和第二n阱的一部分重叠。存储部p阱被放置在第一n阱中，使得其与浮栅电极部分重叠。在该非易失性存储单元中，通过向第二n阱施加正电压来擦除存储器信息，以将浮栅中的电子放电到第二n阱。

5. 发明授权

US08076192B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08076192B2
公开(公告)日：2011-12-13
申请号：US12563326
申请日：2009-09-21
申请人： Yasuhiro Taniguchi , Kazuyoshi Shiba
发明人： Yasuhiro Taniguchi , Kazuyoshi Shiba
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573
摘要： Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.
摘要翻译：提供一种半导体器件的制造方法，其包括在半导体衬底上形成栅极绝缘膜，电荷存储膜，绝缘膜，多晶硅膜，氧化硅膜，氮化硅膜和帽绝缘膜的膜堆叠; 通过光刻和蚀刻从低击穿电压MISFET形成区域和高击穿电压MISFET形成区域去除膜堆叠; 在半导体衬底上形成栅极绝缘膜，多晶硅膜和帽绝缘膜，在低击穿电压MISFET形成区域和高击穿电压MISFET形成区域中形成栅电极，然后在存储器单元形成区域中形成栅电极。通过以不同的步骤形成第一MISFET和第二MISFET的栅极的半导体器件的制造技术，本发明使得可以提供具有改善的可靠性的第一MISFET和第二MISFET。

6. 发明申请

US20100009529A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100009529A1
公开(公告)日：2010-01-14
申请号：US12563326
申请日：2009-09-21
申请人： Yasuhiro Taniguchi , Kazuyoshi Shiba
发明人： Yasuhiro Taniguchi , Kazuyoshi Shiba
IPC分类号： H01L21/28 , H01L21/8238
CPC分类号： H01L21/823462 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573
摘要： Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.
摘要翻译：提供一种半导体器件的制造方法，其包括在半导体衬底上形成栅极绝缘膜，电荷存储膜，绝缘膜，多晶硅膜，氧化硅膜，氮化硅膜和帽绝缘膜的膜堆叠; 通过光刻和蚀刻从低击穿电压MISFET形成区域和高击穿电压MISFET形成区域去除膜堆叠; 在半导体衬底上形成栅极绝缘膜，多晶硅膜和帽绝缘膜，在低击穿电压MISFET形成区域和高击穿电压MISFET形成区域中形成栅电极，然后在存储器单元形成区域中形成栅电极。通过以不同的步骤形成第一MISFET和第二MISFET的栅极的半导体器件的制造技术，本发明使得可以提供具有改善的可靠性的第一MISFET和第二MISFET。

7. 发明授权

US07466599B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07466599B2
公开(公告)日：2008-12-16
申请号：US11925106
申请日：2007-10-26
申请人： Kazuyoshi Shiba , Yasuhiro Taniguchi , Yasushi Oka
发明人： Kazuyoshi Shiba , Yasuhiro Taniguchi , Yasushi Oka
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , G11C2216/10 , H01L27/112
摘要： Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and −9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.
摘要翻译：提供了具有较少元件劣化和良好的数据保存性能的非易失性存储器。在通过互补型MISFET的制造步骤形成的非易失性存储器中，而不添加另外的附加步骤，通过将9V施加到n型阱，9V到ap型半导体区域，并将-9V施加到另一个p型，进行数据擦除半导体区域，并设置数据写入和擦除MISFET和数据读取MISFET的源极和漏极，其处于开放电位，以通过FN隧穿从栅电极发射电子。此时，通过向其中形成有电容元件的p阱施加负电压并向其上形成有MISFET的p阱施加正电压，可以在足够低的电压下确保数据擦除操作所需的电位差不会造成门破损。

8. 发明申请

US20070296030A1 Semiconductor integrated circuit device having deposited layer for gate insulation 有权
公开(公告)号：US20070296030A1
公开(公告)日：2007-12-27
申请号：US11848992
申请日：2007-08-31
申请人： Shoji SHUKURI , Norio Suzuki , Yasuhiro Taniguchi
发明人： Shoji SHUKURI , Norio Suzuki , Yasuhiro Taniguchi
IPC分类号： H01L29/76
CPC分类号： H01L21/823456 , H01L21/28185 , H01L21/28194 , H01L21/823462 , H01L21/823481 , H01L21/8238 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.

9. 发明授权

US06711061B2 Non-volatile semiconductor memory device for selectively re-checking word lines 有权
标题翻译：用于选择性地重新检查字线的非易失性半导体存储器件
公开(公告)号：US06711061B2
公开(公告)日：2004-03-23
申请号：US10223488
申请日：2002-08-20
申请人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
发明人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C8/08 , G11C16/12 , G11C16/3404
摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.
摘要翻译：一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。为每个字线提供字锁存电路，并且在所选择的存储器块中为每个字线管理每个存储器单元的阈值电压。每个字锁存电路由多个字线共享，以便减少所需的芯片面积。为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

10. 发明授权

US06559012B2 Method for manufacturing semiconductor integrated circuit device having floating gate and deposited film 有权
公开(公告)号：US06559012B2
公开(公告)日：2003-05-06
申请号：US09961301
申请日：2001-09-25
申请人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
发明人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
IPC分类号： H01L21336
CPC分类号： H01L21/823456 , H01L21/28185 , H01L21/28194 , H01L21/823462 , H01L21/823481 , H01L21/8238 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式