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1. 发明授权

US4251859A Data processing system with an enhanced pipeline control 失效
标题翻译：数据处理系统具有增强的流水线控制
公开(公告)号：US4251859A
公开(公告)日：1981-02-17
申请号：US957688
申请日：1978-11-06
申请人： Tsugio Momose , Akira Fujita , Kanji Kubo
发明人： Tsugio Momose , Akira Fujita , Kanji Kubo
IPC分类号： G06F9/28 , G06F9/22 , G06F9/38
CPC分类号： G06F9/3836
摘要： A data processing system, for executing each instruction, by carrying out a plurality of successive partial processing operations, begins to process the first partial processing operation of an instruction succeeding a defeat overlap instruction before execution of the defeat overlap instruction is finished in response to the detection that a predetermined number of machine cycles is further required for the complete execution of the defeat overlap instruction.
摘要翻译：用于通过执行多个连续的部分处理操作来执行每个指令的数据处理系统开始处理在执行失败重叠指令之前的失败重叠指令之后的指令的第一部分处理操作，以响应于检测到完全执行失败重叠指令还需要预定数量的机器周期。

2. 发明授权

US4500959A Apparatus for invalidating the content of an instruction buffer by program store compare check 失效
标题翻译：用于通过程序存储比较检查使指令缓冲器的内容无效的装置
公开(公告)号：US4500959A
公开(公告)日：1985-02-19
申请号：US375587
申请日：1982-05-06
申请人： Kanji Kubo , Tsugio Momose , Chikahiko Izumi
发明人： Kanji Kubo , Tsugio Momose , Chikahiko Izumi
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3812
摘要： In a data processing system having an instruction buffer, inconsistency between an instruction stored in a main memory and the same instruction present in the instruction buffer occurs at the time of a store operation to the memory if the instruction supplied to the store area of the main memory previously has been prefetched to and is present in the instruction buffer. The changing in the memory of the content of the instruction prefetched to the instruction buffer and the fact that the changed instruction is about to be executed are detected on the basis of the instruction fetch address of an instruction to be fetched from the memory to the instruction buffer, the instruction address of the next instruction to be executed, information concerning the byte position at which the instruction to be executed is stored, the store address at which the changed instruction is stored in the main storage and information concerning the byte position in the main storage of the instruction which is changed by the store operation. When the execution of the instructions proceeds to the changed instruction, the content of the instruction buffer is invalidated.
摘要翻译：在具有指令缓冲器的数据处理系统中，存储在主存储器中的指令与存储在指令缓冲器中的相同指令之间的不一致在存储操作时发生到存储器，如果提供给主存储器的存储区域的指令先前已经存储了存储在指令缓冲器中的存储器。基于从存储器提取的指令的指令获取地址到指令，检测预先指定到指令缓冲器的指令的内容的存储器的改变以及要改变的指令将被执行的事实的改变缓冲器，要执行的下一条指令的指令地址，存储有要执行的指令的字节位置的信息，改变的指令存储在主存储器中的存储地址以及关于在主存储器中的字节位置的信息由存储操作改变的指令的主存储。当指令的执行进行到改变的指令时，指令缓冲器的内容无效。

3. 发明授权

US4206346A System for gathering data representing the number of event occurrences 失效
标题翻译：用于收集表示事件发生次数的数据的系统
公开(公告)号：US4206346A
公开(公告)日：1980-06-03
申请号：US827361
申请日：1977-08-24
申请人： Toshio Hirosawa , Tsugio Momose , Shigeo Nagashima
发明人： Toshio Hirosawa , Tsugio Momose , Shigeo Nagashima
IPC分类号： G07C3/00 , G01D21/00 , G06F11/34 , G06F17/40 , G06M1/00 , G06M3/00 , G06M7/00 , G06M3/08 , G07C3/10
CPC分类号： G06F11/3409 , G06F11/3476 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： A gathering system in an electronic computer including detecting means for detecting the occurrences of each of a plurality of events, a counter group having a plurality of counters each of which counts the number of occurrences of corresponding event until the number thereof becomes 2.sup.l, a storage having a plurality of memory areas, each storing 2.sup.K.multidot.l occurrences of the corresponding event and a processing unit for gathering data representative of the number of occurrences of each of the events from the counter and the storage unit.
摘要翻译：一种电子计算机中的收集系统，包括用于检测多个事件中的每一个的发生的检测装置，具有多个计数器的计数器组，每个计数器对相应事件的发生次数进行计数，直到其数量变为2l，具有多个存储区域，每个存储区域存储相应事件的2K×1次出现;以及处理单元，用于从计数器和存储单元收集表示每个事件的出现次数的数据。

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