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1. 发明授权

US07779312B2 Built-in redundancy analyzer and method for redundancy analysis 有权
标题翻译：内置冗余分析器和冗余分析方法
公开(公告)号：US07779312B2
公开(公告)日：2010-08-17
申请号：US11837721
申请日：2007-08-13
申请人： Tsu-Wei Tseng , Chih-Chiang Hsu , Jin-Fu Li , Chien-Yuan Pao
发明人： Tsu-Wei Tseng , Chih-Chiang Hsu , Jin-Fu Li , Chien-Yuan Pao
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/16 , G11C29/44 , G11C29/70 , G11C2029/0401
摘要： A built-in redundancy analyzer and a redundancy analysis method thereof for a chip having a plurality of repairable memories are provided. The method includes the following steps. First, the identification code of a repairable memory containing a fault (“fault memory” for short) is identified and a parameter is provided according to the identification code. The parameter includes the length of row address, the length of column address, the length of word, the number of redundancy rows, and the number of redundancy columns of the fault memory. Since the parameter of every individual repairable memory is different, the fault location is converted into a general format according to the parameter for easier processing. A redundancy analysis is then performed according to the parameter and the converted fault location, and the analysis result is converted from the general format to the format of the fault memory and output to the fault memory.
摘要翻译：提供了一种用于具有多个可修复存储器的芯片的内置冗余分析器及其冗余分析方法。该方法包括以下步骤。首先，识别包含故障的可修复存储器的识别码（简称为“故障存储器”），并根据识别码提供参数。该参数包括行地址的长度，列地址的长度，字的长度，冗余行的数量以及故障存储器的冗余列数。由于每个可修复存储器的参数不同，所以根据参数将故障位置转换为一般格式，便于处理。然后根据参数和转换的故障位置执行冗余分析，并将分析结果从通用格式转换为故障存储器的格式，并输出到故障存储器。

2. 发明申请

US20090049333A1 BUILT-IN REDUNDANCY ANALYZER AND METHOD FOR REDUNDANCY ANALYSIS 有权
标题翻译：内置冗余分析器和冗余分析方法
公开(公告)号：US20090049333A1
公开(公告)日：2009-02-19
申请号：US11837721
申请日：2007-08-13
申请人： Tsu-Wei Tseng , Chih-Chiang Hsu , Jin-Fu Li , Chien-Yuan Pao
发明人： Tsu-Wei Tseng , Chih-Chiang Hsu , Jin-Fu Li , Chien-Yuan Pao
IPC分类号： G06F11/22
CPC分类号： G11C29/4401 , G11C29/16 , G11C29/44 , G11C29/70 , G11C2029/0401
摘要： A built-in redundancy analyzer and a redundancy analysis method thereof for a chip having a plurality of repairable memories are provided. The method includes the following steps. First, the identification code of a repairable memory containing a fault (“fault memory” for short) is identified and a parameter is provided according to the identification code. The parameter includes the length of row address, the length of column address, the length of word, the number of redundancy rows, and the number of redundancy columns of the fault memory. Since the parameter of every individual repairable memory is different, the fault location is converted into a general format according to the parameter for easier processing. A redundancy analysis is then performed according to the parameter and the converted fault location, and the analysis result is converted from the general format to the format of the fault memory and output to the fault memory.
摘要翻译：提供了一种用于具有多个可修复存储器的芯片的内置冗余分析器及其冗余分析方法。该方法包括以下步骤。首先，识别包含故障的可修复存储器的识别码（简称为“故障存储器”），并根据识别码提供参数。该参数包括行地址的长度，列地址的长度，字的长度，冗余行的数量以及故障存储器的冗余列数。由于每个可修复存储器的参数不同，所以根据参数将故障位置转换为一般格式，便于处理。然后根据参数和转换的故障位置执行冗余分析，并将分析结果从通用格式转换为故障存储器的格式，并输出到故障存储器。

3. 发明申请

US20090097342A1 BUILT-IN SELF REPAIR CIRCUIT FOR A MULTI-PORT MEMORY AND METHOD THEREOF 失效
标题翻译：用于多端口存储器的内置自修复电路及其方法
公开(公告)号：US20090097342A1
公开(公告)日：2009-04-16
申请号：US11870169
申请日：2007-10-10
申请人： Tsu-Wei Tseng , Yu-Jen Huang , Chun-Hsien Wu , Jin-Fu Li , Chien-Yuan Pao
发明人： Tsu-Wei Tseng , Yu-Jen Huang , Chun-Hsien Wu , Jin-Fu Li , Chien-Yuan Pao
IPC分类号： G11C29/12
CPC分类号： G11C29/44 , G11C8/16 , G11C29/4401 , G11C29/808
摘要： A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test generates a port-specific fault candidate according to the fault location. If a port-specific fault candidate is generated, the DLM generates a defect location based on the fault location and provides the defect location to the TAM so that the TAM can determine how to repair the repairable multi-port memory according to the defect location. If no port-specific fault candidate is generated in the test, the TAM determines how to repair the repairable multi-port memory according to the fault location.
摘要翻译：提供了一种用于多端口存储器的内置自修复（BISR）电路及其方法。该电路包括测试和分析模块（TAM）和耦合到TAM的缺陷定位模块（DLM）。 TAM测试可修复的多端口存储器以产生故障位置，并根据故障位置确定测试是否生成端口特定故障候选。如果生成了特定于端口的故障候选，则DLM根据故障位置生成缺陷位置，并向TAM提供缺陷位置，以便TAM根据缺陷位置确定如何修复可修复的多端口存储器。如果在测试中没有生成端口特定的故障候选，则TAM根据故障位置确定如何修复可修复的多端口存储器。

4. 发明授权

US07596728B2 Built-in self repair circuit for a multi-port memory and method thereof 失效
标题翻译：用于多端口存储器的内置自修复电路及其方法
公开(公告)号：US07596728B2
公开(公告)日：2009-09-29
申请号：US11870169
申请日：2007-10-10
申请人： Tsu-Wei Tseng , Yu-Jen Huang , Chun-Hsien Wu , Jin-Fu Li , Chien-Yuan Pao
发明人： Tsu-Wei Tseng , Yu-Jen Huang , Chun-Hsien Wu , Jin-Fu Li , Chien-Yuan Pao
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/44 , G11C8/16 , G11C29/4401 , G11C29/808
摘要： A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test generates a port-specific fault candidate according to the fault location. If a port-specific fault candidate is generated, the DLM generates a defect location based on the fault location and provides the defect location to the TAM so that the TAM can determine how to repair the repairable multi-port memory according to the defect location. If no port-specific fault candidate is generated in the test, the TAM determines how to repair the repairable multi-port memory according to the fault location.
摘要翻译：提供了一种用于多端口存储器的内置自修复（BISR）电路及其方法。电路包括测试和分析模块（TAM）和耦合到TAM的缺陷定位模块（DLM）。 TAM测试可修复的多端口内存以产生故障位置，并确定测试是否根据故障位置生成端口特定的故障候选。如果生成了特定于端口的故障候选，则DLM根据故障位置生成缺陷位置，并向TAM提供缺陷位置，以便TAM根据缺陷位置确定如何修复可修复的多端口存储器。如果在测试中没有生成端口特定的故障候选，则TAM根据故障位置确定如何修复可修复的多端口存储器。

5. 发明授权

US06459638B1 Built-in programmable self-diagnostic circuit for SRAM unit 失效
标题翻译：用于SRAM单元的内置可编程自诊断电路
公开(公告)号：US06459638B1
公开(公告)日：2002-10-01
申请号：US09901371
申请日：2001-07-09
申请人： Chi-Feng Wu , Chih-Wea Wang , Jin-Fu Li , Cheng-Wen Wu , Chung-Chiang Teng , Chih-Kang Chiu
发明人： Chi-Feng Wu , Chih-Wea Wang , Jin-Fu Li , Cheng-Wen Wu , Chung-Chiang Teng , Chih-Kang Chiu
IPC分类号： G11C700
CPC分类号： G11C29/12 , G11C29/44
摘要： A built-in programmable self-diagnostic circuit for finding and locating faults in a static random access memory (SRAM) unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The circuit uses either internal test instructions or pre-programmed test instructions to test the SRAM unit so that the exact location of any fault in the SRAM unit can be found and subsequently repaired.
摘要翻译：内置可编程自诊断电路，用于在静态随机存取存储器（SRAM）单元中查找和定位故障。该电路包括多个复用器，解复用器，测试码型发生器，故障定位指示器和控制器。该电路使用内部测试指令或预编程的测试指令来测试SRAM单元，以便可以找到并随后修复SRAM单元中任何故障的确切位置。

6. 发明授权

US06529430B2 Built-in programmable self-diagnostic circuit for SRAM unit 失效
公开(公告)号：US06529430B2
公开(公告)日：2003-03-04
申请号：US10163660
申请日：2002-06-04
申请人： Chi-Feng Wu , Chih-Wea Wang , Jin-Fu Li , Cheng-Wen Wu , Chung-Chiang Teng , Chih-Kang Chiu
发明人： Chi-Feng Wu , Chih-Wea Wang , Jin-Fu Li , Cheng-Wen Wu , Chung-Chiang Teng , Chih-Kang Chiu
IPC分类号： G11C700
CPC分类号： G11C29/12 , G11C29/44
摘要： A built-in programmable self-diagnostic circuit for finding and locating faults in a static random access memory (SRAM) unit. The circuit includes a plurality of multiplexers, a demultiplexer, a test pattern generator, a fault location indicator and a controller. The circuit uses either internal test instructions or pre-programmed test instructions to test the SRAM unit so that the exact location of any fault in the SRAM unit can be found and subsequently repaired.

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