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1. 发明授权

US4845728A VLSI binary updown counter 失效
标题翻译： VLSI二进制递减计数器
公开(公告)号：US4845728A
公开(公告)日：1989-07-04
申请号：US143434
申请日：1988-01-13
申请人： Trieu-Kie Truong , In-Shek Hsu , Irving S. Reed
发明人： Trieu-Kie Truong , In-Shek Hsu , Irving S. Reed
IPC分类号： H03K23/44
CPC分类号： H03K23/44
摘要： A pipeline binary updown counter is comprised of simple stages that may be readily replicated. Each stage is defined by the Boolean logic equationA.sub.n (t)=A.sub.n (t-1).sym.[(U.multidot.P.sub.n)+(D.multidot.Q.sub.n)]where A.sub.n (t) denotes the value of the nth bit at time t. The input to the counter has three values represented by two binary signals U and D such that if both are zero, the input is zero, if U=0 and D=1, the input is -1 and if U=1 and D=0, the input is +1. P.sub.n represents a product of A.sub.k 's for 1.ltoreq.k.ltoreq.-1, while Q.sub.n represents the product of A's for 1.ltoreq.k.ltoreq.n-1, where A.sub.k is the complement of A.sub.k and P.sub.n and Q.sub.n are expressed as the following two equationsP.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1Q.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1which can be written in recursion form asP.sub.n =P.sub.n-1 .multidot.A.sub.n-1Q.sub.n =Q.sub.n-1 .multidot.A.sub.n-1with the initial values P.sub.1 =1 and Q.sub.1 =1.
摘要翻译：管道二进制递减计数器由易于复制的简单阶段组成。每个阶段由布尔逻辑方程An（t）= An（t-1）（+）[（UxPn）+（DxQn）]定义，其中An（t）表示时间t的第n位的值。计数器的输入具有由两个二进制信号U和D表示的三个值，使得如果两者都为零，则输入为零，如果U = 0且D = 1，则输入为-1，如果U = 1且D = 0，输入为+1。 Pn表示1的k i = 1的乘积，而Q n表示1

2. 发明授权

US4907233A VLSI single-chip (255,223) Reed-Solomon encoder with interleaver 失效
标题翻译：具有交错器的VLSI单芯片（255,223）Reed-Solomon编码器
公开(公告)号：US4907233A
公开(公告)日：1990-03-06
申请号：US195226
申请日：1988-05-18
申请人： Leslie J. Deutsch , In-Shek Hsu , Trieu-Kie Truong , Irving S. Reed
发明人： Leslie J. Deutsch , In-Shek Hsu , Trieu-Kie Truong , Irving S. Reed
IPC分类号： H03M13/15 , H03M13/29
CPC分类号： H03M13/159 , H03M13/1515 , H03M13/27 , H03M13/2903 , H03M13/293 , H03M13/2936
摘要： A concatenated coding system consisting of a (255,223) Reed-Solomon outer code and a convolutional inner code is provided with either a block of preinterleaved frames or an interleaver of frames in a block of data symbols to be coded in the outer decoder. By interleaving, errors are constrained to occur in only one symbol in a frame, which can be corrected by the Reed-Solomon outer decoder. After transmission and inner decoding, the data symbols are deinterleaved for outer decoding. Instead of preinterleaving at the source, or interleaving before inner encoding, the frames of data symbols may be interleaved at the receiver after inner decoding and then combined with the inner decoded check symbols for outer decoding. The outer encoder is a bit-serial Reed-Solomon encoder with programmable interleaving, and the inner decoder is a Viterbi decoder.
摘要翻译：由（255,223）里德 - 所罗门外码和卷积内码组成的级联编码系统在外解码器中提供要编码的数据符号块中的预先剪切的帧或帧的交织器。通过交错，错误被限制在帧中仅一个符号中，这可以由里德 - 所罗门外部解码器校正。在传输和内部解码之后，数据符号被去交织用于外部解码。在内部编码之前，或者在内部编码之前进行交织，而不是在内部编码之前进行交织，数据符号的帧可以在内部解码之后在接收机处进行交织，然后与用于外部解码的内部解码的检查符号组合。外部编码器是具有可编程交织的位串行里德 - 所罗门编码器，内部解码器是维特比解码器。

3. 发明授权

US5130990A VLSI architecture for a Reed-Solomon decoder 失效
标题翻译：用于Reed-Solomon解码器的VLSI架构
公开(公告)号：US5130990A
公开(公告)日：1992-07-14
申请号：US480449
申请日：1990-02-15
申请人： In-Shek Hsu , Trieu-Kie Truong
发明人： In-Shek Hsu , Trieu-Kie Truong
IPC分类号： G06F11/10 , H03M13/15
CPC分类号： G06F11/10 , H03M13/151
摘要： A basic single-chip building block for a RS decoder system is partitioned into a plurality of sections the first of which consists of a plurality of syndrome subcells each of which contains identical standard-basis finite-field multipliers that are programmable between 10-bit and 8-bit operation. A desired number of basic building blocks may be assembled to provide a RS decoder of any syndrome subcell size that is programmable between 10-bit and 8-bit operation.
摘要翻译：用于RS解码器系统的基本单芯片构建块被划分成多个部分，其中第一部分由多个校正子子单元组成，每个子单元包含相同的基于标准的有限域乘法器，其可在10位和 8位操作。可以组合所需数量的基本构建块以提供可在10位和8位操作之间编程的任何校正子子单元大小的RS解码器。

4. 发明授权

US4868828A Architecture for time or transform domain decoding of reed-solomon codes 失效
标题翻译：对于reed-solomon码的时间或变换域解码的架构
公开(公告)号：US4868828A
公开(公告)日：1989-09-19
申请号：US105101
申请日：1987-10-05
申请人： Howard M. Shao , Trieu-Kie Truong , In-Shek Hsu , Leslie J. Deutsch
发明人： Howard M. Shao , Trieu-Kie Truong , In-Shek Hsu , Leslie J. Deutsch
IPC分类号： H03M13/15
CPC分类号： H03M13/151
摘要： Two pipeline (255,233) RS decoders, one a time domain decoder and the other a transform domain decoder, use the same first part to develop an errata locator polynomial .tau.(x), and an errata evaluator polynominal A(x). Both the time domain decoder and transform domain decoder have a modified GCD that uses an input multiplexer and an output demultiplexer to reduce the number of GCD cells required. The time domain decoder uses a Chien search and polynomial evaluator on the GCD outputs .tau.(x) and A(x), for the final decoding steps, while the transform domain decoder uses a transform error pattern algorithm operating on .tau.(x) and the initial syndrome computation S(x), followed by an inverse transform algorithm in sequence for the final decoding steps prior to adding the received RS coded message to produce a decoded output message.
摘要翻译：两个流水线（255,233）RS解码器，一个时域解码器，另一个是变换域解码器，使用相同的第一部分开发勘误定位多项式tau（x）和勘误评估器多项式A（x）。时域解码器和变换域解码器都具有使用输入多路复用器和输出解复用器的修改的GCD来减少所需的GCD单元的数量。时域解码器在最终解码步骤中对GCD输出τ（x）和A（x）使用Chien搜索和多项式求值器，而变换域解码器使用在tau（x）上操作的变换误差模式算法，并且初始校正子计算S（x），之后是在添加所接收的RS编码消息之前的最终解码步骤的顺序的逆变换算法以产生解码的输出消息。

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