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1. 发明授权

US07155576B1 Pre-fetching and invalidating packet information in a cache memory 有权
标题翻译：在高速缓冲存储器中预取和使分组信息无效
公开(公告)号：US07155576B1
公开(公告)日：2006-12-26
申请号：US10446021
申请日：2003-05-27
申请人： Trevor S. Garner , William R. Lee , Martin W. Hughes
发明人： Trevor S. Garner , William R. Lee , Martin W. Hughes
IPC分类号： G06F12/00 , G06F15/16
CPC分类号： G06F12/0862
摘要： A technique for managing a cache memory coupled to an intermediate node's processor. Packets acquired by the intermediate node that are destined for processing by the processor are tracked, without the processor's intervention, to determine if the processor is lagging in processing the acquired packets. If so, data associated with unprocessed packets are pre-fetched from an external memory and placed in the cache memory without the processor's intervention. Moreover, packets destined for processing by the processor and placed into the cache memory are tracked, without the processor's intervention, to determine if the processor has, in fact, completed the processing of those packets. If so, data contained in the cache memory that is associated with the processed packets are invalidated, again without the processor's intervention.
摘要翻译：一种用于管理耦合到中间节点处理器的高速缓冲存储器的技术。在处理器干预的情况下，跟踪由中间节点获取的目的地由处理器处理的数据包，以确定处理器是否滞后于处理所获取的数据包。如果是这样，与未处理的数据包相关联的数据将从外部存储器预取，并放置在高速缓冲存储器中，而无需处理器的干预。而且，由处理器进行处理并被放置在高速缓冲存储器中的分组被跟踪，而无需处理器的介入，以确定处理器实际上是否完成了那些分组的处理。如果是这样，与处理的数据包相关联的高速缓冲存储器中包含的数据无效，无需处理器的干预。

2. 发明授权

US07302548B1 System and method for communicating in a multi-processor environment 有权
标题翻译：用于在多处理器环境中通信的系统和方法
公开(公告)号：US07302548B1
公开(公告)日：2007-11-27
申请号：US10174716
申请日：2002-06-18
申请人： John W. Mitten , William R. Lee , Trevor S. Garner , Robert L. King
发明人： John W. Mitten , William R. Lee , Trevor S. Garner , Robert L. King
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/167
摘要： A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination processor. The bit is positioned in a send register associated with the originating processor and transposed from the send register of the originating processor to a receive register of the destination processor. An interrupt signal is then generated in response to the bit being transposed.
摘要翻译：提供了一种用于在多处理器环境中进行通信的方法，其包括在与待传送到目的地处理器的消息相关联的发起处理器处生成位。该位位于与始发处理器相关联的发送寄存器中，并从发起处理器的发送寄存器转发到目标处理器的接收寄存器。然后响应于该位被转置而产生中断信号。

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