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1. 发明授权

US5907699A Microcomputer with two oscillators of different frequencies selectable by a reset signal set by an instruction or by an overflow signal of a counter 失效
标题翻译：具有不同频率的两个振荡器的微型计算机可以通过由指令或计数器的溢出信号设置的复位信号来选择
公开(公告)号：US5907699A
公开(公告)日：1999-05-25
申请号：US970536
申请日：1997-11-14
申请人： Toyokatsu Nakajima
发明人： Toyokatsu Nakajima
IPC分类号： G06F1/06 , G06F1/04 , G06F1/32 , G06F1/26
CPC分类号： G06F1/04 , G06F1/3203 , G06F1/3237 , Y02B60/1217 , Y02B60/1221
摘要： A microcomputer incorporating two oscillation circuits for generating clocks having different frequencies, which can be driven even when an oscillator is connected only to one of the oscillation circuits, by counting the number of clock pulses of the first or the second oscillation circuit, and selecting the clock of the first or the second oscillation circuit according to the data latched in a latch circuit that is set by an overflow signal outputted when the count value overflows.
摘要翻译：一种微型计算机，包括用于产生具有不同频率的时钟的两个振荡电路，即使当振荡器仅连接到一个振荡电路时，也可以通过对第一或第二振荡电路的时钟脉冲数进行计数来选择根据锁存在由计数值溢出时输出的溢出信号而设定的锁存电路的数据，第一或第二振荡电路的时钟。

2. 发明授权

US5721887A Microcomputer including a circuit for generating a reset signal when the supply voltage is below a threshold level 失效
标题翻译：微电脑包括当电源电压低于阈值电平时产生复位信号的电路
公开(公告)号：US5721887A
公开(公告)日：1998-02-24
申请号：US498814
申请日：1995-07-06
申请人： Toyokatsu Nakajima
发明人： Toyokatsu Nakajima
IPC分类号： G06F15/78 , G06F1/24 , G06F1/30 , H01L21/822 , H01L27/04
CPC分类号： G06F1/305 , G06F1/24
摘要： A microcomputer in which a voltage drop in a power source is detected by a voltage detecting circuit, and a capacitor is connected to a first power source and/or a second power source on the basis of a detection signal of said detecting circuit thereby to be charged/discharged, so that a reset signal is generated. The supply of a clock signal is controlled on the basis of said detection signal. When a source voltage of the microcomputer is found to be lower than a reference voltage but recovering in a short time, it is possible to resume a programmed operation from a temporary cut-off state without initializing the program.
摘要翻译：一种微电脑，其中通过电压检测电路检测电源中的电压降，并且电容器基于所述检测电路的检测信号连接到第一电源和/或第二电源，从而为充电/放电，从而产生复位信号。基于所述检测信号来控制时钟信号的供给。当发现微型计算机的源电压低于参考电压但是在短时间内恢复时，可以在不初始化程序的情况下从临时截止状态恢复编程操作。

3. 发明授权

US5331324A A/D converter 失效
标题翻译： A / D转换器
公开(公告)号：US5331324A
公开(公告)日：1994-07-19
申请号：US21432
申请日：1993-02-23
申请人： Toyokatsu Nakajima
发明人： Toyokatsu Nakajima
IPC分类号： G06F3/05 , H03M1/12 , H03M1/46
CPC分类号： H03M1/1225 , H03M1/46
摘要： To accept a plurality of starting factors without the use of a CPU and improve the real-time processing speed of A/D conversion, the same number of channel selection registers, mode registers and conversion result storage registers as the number of starting factors are provided and divided into groups according to the types of starting factors, and a control circuit for specifying a register group for a starting factor when the factor is generated is also provided.
摘要翻译：为了在不使用CPU的情况下接受多个启动因素并提高A / D转换的实时处理速度，提供相同数量的通道选择寄存器，模式寄存器和转换结果存储寄存器作为启动因子的数量并根据启动因素的种类分为组，还提供用于在产生因子时指定起始因子的寄存器组的控制电路。

4. 发明授权

US5966086A Microcomputer having an output circuit with a resistor ladder 失效
标题翻译：微电脑具有带梯形电阻的输出电路
公开(公告)号：US5966086A
公开(公告)日：1999-10-12
申请号：US933276
申请日：1997-09-18
申请人： Kenji Kubo , Toyokatsu Nakajima , Hiroyuki Maemura
发明人： Kenji Kubo , Toyokatsu Nakajima , Hiroyuki Maemura
IPC分类号： G06F3/00 , G06F1/30 , G06F11/00 , G06F15/78 , H03M1/00
CPC分类号： G06F1/305 , G06F11/00
摘要： A microcomputer includes an operation circuit for performing an operation using a reference voltage. A reference voltage input terminal receives the reference voltage from an external device. An output circuit outputs an output signal from the microcomputer to an external destination. The level of the output signal depends on the reference voltage input through the reference voltage input terminal.
摘要翻译：微型计算机包括用于使用参考电压进行操作的操作电路。参考电压输入端子从外部设备接收参考电压。输出电路将来自微型计算机的输出信号输出到外部目的地。输出信号的电平取决于通过参考电压输入端子输入的参考电压。

5. 发明授权

US5638075A Successive approximation ADC with rounding to vary bit number output 失效
标题翻译：连续近似ADC，具有舍入以改变位数输出
公开(公告)号：US5638075A
公开(公告)日：1997-06-10
申请号：US503356
申请日：1995-07-17
申请人： Toyokatsu Nakajima
发明人： Toyokatsu Nakajima
IPC分类号： H03M1/46 , H03M1/00
CPC分类号： H03M1/462
摘要： An analog/digital (A/D) converter includes a sequential approximation register (SA register) having a plurality of bits for storing the results of conversion in digits and an incrementor having a smaller number of bits than that of the SA register. The incrementor increments a portion of the results of conversion on the basis of the result of conversion of at least one bit in the SA register so as to minimize an error in the A/D conversion of a smaller number of bits than that of the SA register.
摘要翻译：模拟/数字（A / D）转换器包括具有用于存储数字转换结果的多个位的顺序近似寄存器（SA寄存器）和具有比SA寄存器的位数更少的位数的增量器。增量器根据SA寄存器中至少一个位的转换结果对转换结果的一部分进行增加，从而最小化比SA少的位数的A / D转换中的错误寄存器。

6. 发明授权

US5229770A Analog/digital converter with advanced conversion termination notice 失效
标题翻译：具有高级转换终止通知的模拟/数字转换器
公开(公告)号：US5229770A
公开(公告)日：1993-07-20
申请号：US821669
申请日：1992-01-16
申请人： Toyokatsu Nakajima
发明人： Toyokatsu Nakajima
IPC分类号： H03M1/12 , H03M1/38 , H03M1/46
CPC分类号： H03M1/462
摘要： An analog/digital converter in the present invention compares sequentially with respect to the elapse of time an inputted analog signal with multiple-bit signals corresponding to reference voltages of multiple levels so as to output a digital signal. The analog/digital converter includes a shift register for tracking the termination of the comparisons of each bit signal at every bit with the elapse of time, a selector for sequentially storing in an internal register select shift register bits representing comparison termination signals, and a central processing unit for selecting one of the termination signals stored in the internal register so as to output it to the flag register. The termination signal may be output to the flag register before digital conversion is complete thereby enabling the CPU to prepare to read the final result while digital conversion is still being performed.
摘要翻译：本发明中的模拟/数字转换器相对于输入的模拟信号与多个等级的参考电压的多位信号的时间顺序地进行比较，以输出数字信号。模拟/数字转换器包括一个移位寄存器，用于随着时间的推移跟踪每个位的每个比特信号的比较结束，选择器用于顺序地存储在内部寄存器中，选择移位寄存器比特表示比较终止信号，以及中央处理单元，用于选择存储在内部寄存器中的一个终止信号，以将其输出到标志寄存器。在数字转换完成之前，终止信号可以被输出到标志寄存器，从而使CPU能够准备在仍然执行数字转换的同时读取最终结果。

7. 发明授权

US4937782A Counter control method 失效
标题翻译：计数器控制方法
公开(公告)号：US4937782A
公开(公告)日：1990-06-26
申请号：US142111
申请日：1988-01-11
申请人： Shigeo Mizugaki , Toyokatsu Nakajima , Kikuo Muramatsu
发明人： Shigeo Mizugaki , Toyokatsu Nakajima , Kikuo Muramatsu
IPC分类号： G06F9/30 , G06F1/04 , G06F15/78 , H03K21/38
CPC分类号： H03K21/38
摘要： A counter control method according to the present invention comprising the steps of:(a) allocating switching information corresponding to counters in need of being simultaneously started among switching information each serving to drive a plurality of switching means, to an address (c) of memory means to which operation control means is accessible at a time, and(b) driving said switching means using said switching information so allocated to thereby start said plurality of the counters.
摘要翻译：根据本发明的计数器控制方法包括以下步骤：（a）将与驱动多个切换装置的切换信息中需要同时开始的计数器相对应的切换信息分配给存储器的地址（c）一种操作控制装置一次可访问的装置，以及（b）使用所分配的切换信息驱动所述切换装置，从而启动所述多个计数器。

8. 发明授权

US5632040A Microcomputer having reduced power consumption through impedance control and frequency reduction 失效
标题翻译：微电脑通过阻抗控制和频率降低降低功耗
公开(公告)号：US5632040A
公开(公告)日：1997-05-20
申请号：US564940
申请日：1995-11-30
申请人： Toyokatsu Nakajima
发明人： Toyokatsu Nakajima
IPC分类号： G06F15/78 , G06F1/32 , G06F1/26
CPC分类号： G06F1/324 , G06F1/3203 , Y02B60/1217
摘要： A microcomputer comprising a clock circuit which selects a pulse signal as a system clock of the microcomputer from among a plurality of pulse signals and a power source impedance controlling circuit which controls an impedance between a power input terminal and the units of the microcomputer based on the frequency of the pulse signal selected by the clock circuit to provide the electric power to the units of the microcomputer. The power source impedance controlling circuit controls the impedance such that the power source impedance is made lower as the frequency of the selected pulse signal is higher.
摘要翻译：一种微型计算机，包括：时钟电路，其从多个脉冲信号中选择脉冲信号作为微型计算机的系统时钟;以及电源阻抗控制电路，其基于所述电源输入端子和所述微计算机的单元来控制阻抗由时钟电路选择的脉冲信号的频率，以向微型计算机的单元提供电力。电源阻抗控制电路控制阻抗，使得电源阻抗随着所选脉冲信号的频率较高而变低。

9. 发明授权

US5459851A Dual-port memory with selective read data output prohibition 失效
标题翻译：具有选择性读取数据输出禁止的双端口存储器
公开(公告)号：US5459851A
公开(公告)日：1995-10-17
申请号：US298083
申请日：1994-08-31
申请人： Toyokatsu Nakajima , Mitsuru Sugita
发明人： Toyokatsu Nakajima , Mitsuru Sugita
IPC分类号： G06F12/00 , G11C8/16 , G11C11/41 , G06F12/14 , G06F13/376 , G11C11/407 , G11C11/413
CPC分类号： G11C8/16
摘要： A dual-port memory is interposed between a host system and a slave system in a multiprocessor system, and data transmission between the host system and the slave system is performed through the dual-port memory using first and second input/output ports, the dual-port memory being accessible from the host system and the slave system simultaneously. An address region of the dual-port memory is placed overlapping the address space of an internal memory of the host system, so that no change is needed in programming in the host system, however, data collision may be generated in a region in the address space shared by the internal memory and the dual-port memory. In order to prevent data collision, the dual-port memory includes a memory cell array having a plurality of memory cells, first cell selection circuitry and second cell selection circuitry, and read data output prohibiting circuitry which prohibits data read out from a selected memory cell from being output to the host system. The output of data read out from a portion of the memory cells in the memory array may be prohibited instead.
摘要翻译：双端口存储器插入在多处理器系统中的主机系统和从系统之间，并且通过使用第一和第二输入/输出端口的双端口存储器来执行主机系统和从系统之间的数据传输，双重端口存储器 - 端口存储器可以从主机系统和从系统同时访问。双端口存储器的地址区域与主机系统的内部存储器的地址空间重叠，从而在主机系统的编程中不需要改变，但是可能在地址中的一个区域中产生数据冲突由内部存储器和双端口存储器共享的空间。为了防止数据冲突，双端口存储器包括具有多个存储器单元，第一单元选择电路和第二单元选择电路的存储单元阵列，以及禁止从所选存储单元读出数据的读出数据输出禁止电路从输出到主机系统。可以禁止从存储器阵列中的存储单元的一部分读出的数据的输出。

10. 发明授权

US5341120A Comparison circuit 失效
标题翻译：比较电路
公开(公告)号：US5341120A
公开(公告)日：1994-08-23
申请号：US872573
申请日：1992-04-23
申请人： Toyokatsu Nakajima
发明人： Toyokatsu Nakajima
IPC分类号： G05B1/02 , G05B15/02 , G05B1/03 , G06F7/02
CPC分类号： G05B1/02
摘要： An analog input is compared with a comparison value by an analog comparator to set a comparison result register and comparison is automatically repeated until the value of the register coincides with the value of an expected value storing register. When the both values coincide with each other, an interrupt request signal is outputted and comparison is completed.
摘要翻译：将模拟输入与模拟比较器的比较值进行比较，以设置比较结果寄存器，并自动重复比较，直到寄存器的值与预期值存储寄存器的值一致。当这两个值彼此一致时，输出中断请求信号并完成比较。

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