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1. 发明申请

US20070020781A1 Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program 审中-公开
标题翻译：半导体故障分析装置，故障分析方法和故障分析程序
公开(公告)号：US20070020781A1
公开(公告)日：2007-01-25
申请号：US11409272
申请日：2006-04-24
申请人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta , Masahiro Takeda
发明人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta , Masahiro Takeda
IPC分类号： H01L21/66
CPC分类号： G01N21/956 , G06T7/001 , G06T2207/30148
摘要： A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, a failure analyzer 13 for analyzing a failure of the semiconductor device, and an analysis screen display controller 14 for letting a display device 40 display information about a result of the analysis. The failure analyzer 13 sets an analysis region with reference to the failure observed image P2, and extracts a net passing the analysis region, from a plurality of nets included in a layout of the semiconductor device. This substantializes a semiconductor failure analysis apparatus, analysis method, and analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device.
摘要翻译：失效分析装置10由用于获取半导体装置的故障观察图像P 2的检查信息获取部11，用于获取布局信息的布局信息获取部12，用于分析半导体装置的故障的故障分析部13，以及用于使显示装置40显示关于分析结果的信息的分析屏幕显示控制器14。故障分析器13参照故障观察图像P 2设定分析区域，从包含在半导体装置的布局中的多个网络提取通过分析区域的网络。这实现了能够安全有效地执行半导体器件的故障分析的半导体故障分析装置，分析方法和分析程序。

2. 发明申请

US20070292018A1 Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program 有权
标题翻译：半导体故障分析装置，故障分析方法和故障分析程序
公开(公告)号：US20070292018A1
公开(公告)日：2007-12-20
申请号：US11586721
申请日：2006-10-26
申请人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
发明人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
IPC分类号： G01R31/303
CPC分类号： G01N21/95607 , G01N2021/95615
摘要： A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts as a candidate interconnection for a failure, an interconnection passing an analysis region, out of a plurality of interconnections, using interconnection information to describe a configuration of interconnections in the semiconductor device by a pattern data group of interconnection patterns in respective layers, and, for extracting the candidate interconnection, it performs an equipotential trace of the interconnection patterns using the pattern data group, thereby extracting the candidate interconnection. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.
摘要翻译：失效分析装置10由用于获取半导体器件的故障观察图像P 2的检查信息获取器11，用于获取布局信息的布局信息获取器12以及用于分析故障的故障分析器13组成。故障分析器13通过互连信息提取出故障的候选互连，通过分析区域的互连，使用互连信息，以通过相应的互连模式的图案数据组来描述半导体器件中的互连的配置并且为了提取候选互连，它使用模式数据组来执行互连模式的等势线，从而提取候选互连。这实现了半导体故障分析装置，故障分析方法和故障分析程序，其能够安全有效地执行使用故障观察图像的半导体器件的故障的分析。

3. 发明授权

US07805691B2 Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program 有权
标题翻译：半导体故障分析装置，故障分析方法和故障分析程序
公开(公告)号：US07805691B2
公开(公告)日：2010-09-28
申请号：US11586719
申请日：2006-10-26
申请人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
发明人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
IPC分类号： G06F17/50
CPC分类号： G01R31/311 , G01N21/95607 , G01R31/2894
摘要： A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts candidate nets passing at least one of analysis regions set from the failure observed image, out of a plurality of nets in the semiconductor device, and passage counts of the respective candidate nets through the analysis regions, selects a candidate net with the largest passage count as a first failure net, and selects a second failure net with attention to analysis regions where the first failure net does not pass. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.
摘要翻译：故障分析装置10由用于获取半导体装置的故障观察图像P2的检查信息获取部11，用于获取布局信息的布局信息获取部12以及用于分析故障的故障分析部13构成。故障分析部13从通过半导体装置的多个网络中的故障观察图像，从故障观察图像设定的分析区域中的至少一个以及通过分析区域的各个候选网络的通过计数来提取候补网络，选择候补网络作为第一故障网络的最大通行数，并且选择第二故障网络，注意第一故障网络不通过的分析区域。这实现了半导体故障分析装置，故障分析方法和故障分析程序，其能够安全有效地执行使用故障观察图像的半导体器件的故障的分析。

4. 发明申请

US20070294053A1 Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program 有权
标题翻译：半导体故障分析装置，故障分析方法和故障分析程序
公开(公告)号：US20070294053A1
公开(公告)日：2007-12-20
申请号：US11586719
申请日：2006-10-26
申请人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
发明人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
IPC分类号： G01R31/00
CPC分类号： G01R31/311 , G01N21/95607 , G01R31/2894
摘要： A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts candidate nets passing at least one of analysis regions set from the failure observed image, out of a plurality of nets in the semiconductor device, and passage counts of the respective candidate nets through the analysis regions, selects a candidate net with the largest passage count as a first failure net, and selects a second failure net with attention to analysis regions where the first failure net does not pass. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.
摘要翻译：失效分析装置10由用于获取半导体器件的故障观察图像P 2的检查信息获取器11，用于获取布局信息的布局信息获取器12以及用于分析故障的故障分析器13组成。故障分析部13从通过半导体装置的多个网络中的故障观察图像，从故障观察图像设定的分析区域中的至少一个以及通过分析区域的各个候选网络的通过计数来提取候补网络，选择候补网络作为第一故障网络的最大通行数，并且选择第二故障网络，注意第一故障网络不通过的分析区域。这实现了半导体故障分析装置，故障分析方法和故障分析程序，其能够安全有效地执行使用故障观察图像的半导体器件的故障的分析。

5. 发明申请

US20070290696A1 Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program 审中-公开
标题翻译：半导体故障分析装置，故障分析方法和故障分析程序
公开(公告)号：US20070290696A1
公开(公告)日：2007-12-20
申请号：US11586720
申请日：2006-10-26
申请人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
发明人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
IPC分类号： G01R31/302
CPC分类号： G01R31/303
摘要： A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure of the semiconductor device. The failure analyzer 13 has an analysis region setter for comparing an intensity distribution in the failure observed image with a predetermined intensity threshold to extract a reaction region arising from a failure, and for setting an analysis region used in the failure analysis of the semiconductor device, in correspondence to the reaction region. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.
摘要翻译：故障分析装置10由用于获取半导体器件的故障观察图像P 2的检查信息获取器11，用于获取布局信息的布局信息获取器12以及用于分析半导体器件的故障的故障分析器13构成。故障分析器13具有分析区域设定器，用于将故障观察图像中的强度分布与预定强度阈值进行比较，以提取由故障引起的反应区域，并且用于设定在半导体器件的故障分析中使用的分析区域，对应于反应区域。这实现了半导体故障分析装置，故障分析方法和故障分析程序，其能够安全有效地执行使用故障观察图像的半导体器件的故障的分析。

6. 发明授权

US07865012B2 Semiconductor failure analysis apparatus which acquires a failure observed image, failure analysis method, and failure analysis program 有权
标题翻译：获取故障观察图像，故障分析方法和故障分析程序的半导体故障分析装置
公开(公告)号：US07865012B2
公开(公告)日：2011-01-04
申请号：US11586721
申请日：2006-10-26
申请人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
发明人： Toshiyuki Majima , Akira Shimase , Hirotoshi Terada , Kazuhiro Hotta
IPC分类号： G06K9/00
CPC分类号： G01N21/95607 , G01N2021/95615
摘要： A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts as a candidate interconnection for a failure, an interconnection passing an analysis region, out of a plurality of interconnections, using interconnection information to describe a configuration of interconnections in the semiconductor device by a pattern data group of interconnection patterns in respective layers, and, for extracting the candidate interconnection, it performs an equipotential trace of the interconnection patterns using the pattern data group, thereby extracting the candidate interconnection. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.
摘要翻译：故障分析装置10由用于获取半导体装置的故障观察图像P2的检查信息获取部11，用于获取布局信息的布局信息获取部12以及用于分析故障的故障分析部13构成。故障分析器13通过互连信息提取出故障的候选互连，通过分析区域的互连，使用互连信息，以通过相应的互连模式的图案数据组来描述半导体器件中的互连的配置并且为了提取候选互连，它使用模式数据组来执行互连模式的等势线，从而提取候选互连。这实现了半导体故障分析装置，故障分析方法和故障分析程序，其能够安全有效地执行使用故障观察图像的半导体器件的故障的分析。

7. 发明授权

US07752594B2 Semiconductor failure analysis apparatus, failure analysis method, failure analysis program, and failure analysis system 有权
标题翻译：半导体故障分析装置，故障分析方法，故障分析程序和故障分析系统
公开(公告)号：US07752594B2
公开(公告)日：2010-07-06
申请号：US11409273
申请日：2006-04-24
申请人： Masahiro Takeda , Kazuhiro Hotta
发明人： Masahiro Takeda , Kazuhiro Hotta
IPC分类号： G06F17/50
CPC分类号： G01N21/956 , G06T7/0004 , G06T2207/30148
摘要： A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring at least a pattern image P1 of a semiconductor device, a layout information acquirer 12 for acquiring a layout image P3, a failure analyzer 13 for analyzing a failure of the semiconductor device, and an analysis screen display controller 14 for letting a display device 40 display information about the failure analysis. The analysis screen display controller 14 generates a superimposed image in which the pattern image P1 and the layout image P3 are superimposed, as an image of the semiconductor device to be displayed by the display device 40, and sets a transmittance of the layout image P3 relative to the pattern image P1 in the superimposed image. This substantializes a semiconductor failure analysis apparatus, analysis method, analysis program, and analysis system capable of securely and efficiently carrying out the analysis of the failure of the semiconductor device.
摘要翻译：故障分析装置10由用于获取至少半导体装置的图案图像P1的检查信息获取部11，用于获取布局图像P3的布局信息获取部12，用于分析半导体装置的故障的故障分析部13 以及用于使显示装置40显示关于故障分析的信息的分析屏幕显示控制器14。分析画面显示控制器14生成将图案图像P1和布局图像P3重叠的叠加图像作为要由显示装置40显示的半导体器件的图像，并且将布局图像P3的透射率相对于到叠加图像中的图案图像P1。这实现了能够安全有效地进行半导体器件的故障分析的半导体故障分析装置，分析方法，分析程序和分析系统。

8. 发明申请

US20070011519A1 Semiconductor failure analysis apparatus, failure analysis method, failure analysis program, and failure analysis system 有权
标题翻译：半导体故障分析装置，故障分析方法，故障分析程序和故障分析系统
公开(公告)号：US20070011519A1
公开(公告)日：2007-01-11
申请号：US11409273
申请日：2006-04-24
申请人： Masahiro Takeda , Kazuhiro Hotta
发明人： Masahiro Takeda , Kazuhiro Hotta
IPC分类号： G01R31/28
CPC分类号： G01N21/956 , G06T7/0004 , G06T2207/30148
摘要： A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring at least a pattern image P1 of a semiconductor device, a layout information acquirer 12 for acquiring a layout image P3, a failure analyzer 13 for analyzing a failure of the semiconductor device, and an analysis screen display controller 14 for letting a display device 40 display information about the failure analysis. The analysis screen display controller 14 generates a superimposed image in which the pattern image P1 and the layout image P3 are superimposed, as an image of the semiconductor device to be displayed by the display device 40, and sets a transmittance of the layout image P3 relative to the pattern image P1 in the superimposed image. This substantializes a semiconductor failure analysis apparatus, analysis method, analysis program, and analysis system capable of securely and efficiently carrying out the analysis of the failure of the semiconductor device.
摘要翻译：故障分析装置10由用于获取至少半导体装置的图案图像P 1的检查信息获取部11，用于获取布局图像P 3的布局信息获取部12，用于分析半导体装置的故障的故障分析部13 半导体装置以及用于使显示装置40显示关于故障分析的信息的分析画面显示控制器14。分析画面显示控制器14生成叠加有图案图像P 1和布局图像P 3的叠加图像作为要由显示装置40显示的半导体器件的图像，并且设置布局图像的透射率 P 3相对于叠加图像中的图案图像P 1。这实现了能够安全有效地进行半导体器件的故障分析的半导体故障分析装置，分析方法，分析程序和分析系统。

9. 发明授权

US08047810B2 Double-headed piston type compressor 有权
标题翻译：双头活塞式压缩机
公开(公告)号：US08047810B2
公开(公告)日：2011-11-01
申请号：US12021831
申请日：2008-01-29
申请人： Manabu Sugiura , Akio Saiki , Norikazu Deto , Kazuhiro Hotta
发明人： Manabu Sugiura , Akio Saiki , Norikazu Deto , Kazuhiro Hotta
IPC分类号： F04B1/12 , F04B7/00 , F01B3/00
CPC分类号： F04B27/1018 , F04B39/0027 , F04B39/10
摘要： A double-headed piston type compressor connected with an external device is provided. The compressor includes a plurality of cylinder bore pairs, double-headed pistons, a first rotary valve, a second rotary valve, first suction passages, and second suction passages. In each cylinder bore pair, a first time period from a first top dead center timing, which is timing when the double-headed piston reaches a top dead center in a first compression chamber, to a first communication start timing, which is timing when a first introduction passage starts to communicate with a first suction passage, is different from a second time period from a second top dead center timing, which is timing when the double-headed piston reaches a top dead center in a second compression chamber, to a second communication start timing, which is timing when the second introduction passage starts to communicate with a second suction passages.
摘要翻译：提供与外部装置连接的双头活塞式压缩机。压缩机包括多个气缸孔对，双头活塞，第一旋转阀，第二旋转阀，第一吸入通道和第二吸入通道。在每个气缸孔对中，从第一上死点定时（即双头活塞到达第一压缩室中的上止点的定时）到第一通信开始定时的第一时间段第一引入通道开始与第一吸入通道连通，与第二上死点定时（即双头活塞到达第二压缩室中的上止点的时刻）的第二时间段不同，通信开始定时，其是第二引入通道开始与第二吸入通道连通的定时。

10. 外观设计

USD576179S1 Piston for compressor 有权
标题翻译：活塞式压缩机
公开(公告)号：USD576179S1
公开(公告)日：2008-09-02
申请号：US29286959
申请日：2007-05-23
申请人： Jun Kondo , Hitoshi Inukai , Kazuhiro Hotta , Hiroko Asaoka
设计人： Jun Kondo , Hitoshi Inukai , Kazuhiro Hotta , Hiroko Asaoka

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