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1. 发明授权

US5371702A Block erasable nonvolatile memory device 失效
标题翻译：块可擦除非易失性存储器件
公开(公告)号：US5371702A
公开(公告)日：1994-12-06
申请号：US27489
申请日：1993-03-05
申请人： Hiroto Nakai , Hideo Kato , Kaoru Tokushige , Masamichi Asano , Kazuhisa Kanazawa , Toshio Yamamura
发明人： Hiroto Nakai , Hideo Kato , Kaoru Tokushige , Masamichi Asano , Kazuhisa Kanazawa , Toshio Yamamura
IPC分类号： G11C16/16 , G11C11/34 , G11C7/00
CPC分类号： G11C16/16
摘要： In response to a plurality of address signal input from the outside in sequence, an erase information inputting section controls an erase information holding section corresponding to the batch erase block to be erased so as to hold an erase information data. By repeating this operation in sequence, the erase information data are stored in the erase information holding sections corresponding to the plural batch erase blocks to be erased. Successively, on the basis of the erase information data stored in the erase information holding sections, block erasing sections are activated to erase all the nonvolatile memory cells of each of the corresponding blocks where the erase information data are held. As a result, the erasure operation is achieved for all the batch erase blocks corresponding to the erase information holding sections in each of which the erase information data is held, so that a plurality of batch erase blocks can be erased simulataneously, thus reducing the erasure time, as compared with the prior art memory device.
摘要翻译：响应于从外部依次输入的多个地址信号，擦除信息输入部分控制与待擦除的批量擦除块相对应的擦除信息保持部分，以便保存擦除信息数据。通过依次重复该操作，擦除信息数据被存储在与要擦除的多批擦除块相对应的擦除信息保持部分中。接着，基于存储在擦除信息保持部中的擦除信息数据，块消除部分被激活，以擦除保持擦除信息数据的每个相应块的所有非易失性存储器单元。结果，对于与保持擦除信息数据的擦除信息保持部分相对应的所有批量擦除块实现擦除操作，使得可以同时擦除多个批量擦除块，从而减少擦除与现有技术的存储器件相比。

2. 发明授权

US5436913A Non-volatile semiconductor memory device using successively longer write pulses 失效
标题翻译：使用连续更长写入脉冲的非易失性半导体存储器件
公开(公告)号：US5436913A
公开(公告)日：1995-07-25
申请号：US069911
申请日：1993-06-01
申请人： Toshio Yamamura , Hiroto Nakai , Hideo Kato , Kaoru Tokushige , Masamichi Asano
发明人： Toshio Yamamura , Hiroto Nakai , Hideo Kato , Kaoru Tokushige , Masamichi Asano
IPC分类号： G11C16/34 , G06F11/00
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A non-volatile semiconductor memory device has writing part (203, 205, 209) for writing data in a non-volatile memory cell in response to a write pulse, readout part (419) for reading out data stored in the memory cell, and verification part (207, 210; 417) for verifying to ensure that normal writing has been completed by reading data from the memory cell after each writing. The device repeats writings unless a normal writing can be confirmed by the verification part. At this time, the writing part can vary writing time and in a part of a sequence of repeating writing unless a normal writing can be confirmed, it sets writing time longer for the next writing action than that for one writing action. Since this setting is performed according to constant multiplication, constant increment, or constant multiplication of accumulated value, necessary time for obtaining normal data write can be reduced.
摘要翻译：非挥发性半导体存储器件具有写入部分（203,205,209），用于响应写入脉冲在非易失性存储单元中写入数据，用于读出存储在存储器单元中的数据的读出部分（419）以及验证部件（207,210; 417），用于通过在每次写入之后从存储器单元读取数据来验证以确保正常写入已经完成。设备重复写入，除非验证部分可以确认正常写入。此时，写入部分可以改变写入时间，并且在重复写入序列的一部分中，除非正常写入可以被确认，否则为下一个写入动作设置比一个写入动作的写入时间更长的时间。由于根据常数乘法，常数增量或累积值的常数乘法执行该设置，因此可以减少获得正常数据写入所需的时间。

3. 发明授权

US06418052B1 Nonvolatile semiconductor memory equipped with data latch circuits for transferring one-bit data or multi-bit data 有权
标题翻译：非易失性半导体存储器配备有用于传送一位数据或多位数据的数据锁存电路
公开(公告)号：US06418052B1
公开(公告)日：2002-07-09
申请号：US09976826
申请日：2001-10-12
申请人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
发明人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
IPC分类号： G11C1624
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C2211/5641 , G11C2211/5642
摘要： Data latch circuits are provided corresponding to select memory cells from or into which read or program is executed. The data latch circuits are grouped by two into sets. When 2-bit data is read from or programmed into the select memory cells, one data latch circuit is selected by a select signal, and, when 1-bit data is read or programmed, the two data latch circuits in one set are selected by a select signal. Between one or two selected data latch circuits and a data input/output buffer, data is exchanged. By so doing, changeover between 2-level data and multi-level (4-level or more-level) data concerning program or read of data into or out the memory cells becomes possible.
摘要翻译：数据锁存电路是从执行读取或程序的选择存储器单元提供的。数据锁存电路分为两组。当2位数据从选择存储单元读取或编程到选择存储单元中时，通过选择信号选择一个数据锁存电路，当读取或编程1位数据时，一组中的两个数据锁存电路由选择信号。在一个或两个选择的数据锁存电路和数据输入/输出缓冲器之间，交换数据。通过这样做，有可能在二级数据与有关程序的多级（4级或更多级）数据之间切换或将数据读入或取出存储单元变成可能。

4. 发明授权

US5682346A Nonvolatile semiconductor memory device having suitable writing efficiency 失效
标题翻译：具有合适写入效率的非易失性半导体存储器件
公开(公告)号：US5682346A
公开(公告)日：1997-10-28
申请号：US626256
申请日：1996-03-29
申请人： Toshio Yamamura , Hiroto Nakai , Tomoharu Tanaka
发明人： Toshio Yamamura , Hiroto Nakai , Tomoharu Tanaka
IPC分类号： G11C16/10 , G11C16/30 , G11C11/34
CPC分类号： G11C16/30 , G11C16/10
摘要： According to the present invention, a voltage level for boosting a writing voltage to be supplied to memory cells of a memory cell array, and writing time are optimized in consideration of writing efficiency and a distribution of threshold voltage. A boosting circuit boosts the writing voltage to be supplied to memory cells. A counter counts the number of writing times in accordance with a signal of a timer. The timer outputs the signal used to count the number of writing times at a fixed interval from a first writing time until an arbitrary writing time in counting a predetermined number of writing times by the counter and to count the number of writing times at an interval when the number of writing times is gradually increased after the arbitrary writing time in order to control supplying time of the writing voltage to the memory cells. Additionally, a voltage control circuit gradually divides a boost level due to the boosting circuit in accordance with the arbitrary number of writing times until the writing voltage reaches a predetermined upper limit, and maintains the writing voltage when the writing voltage reaches the predetermined upper limit.
摘要翻译：根据本发明，考虑到写入效率和阈值电压的分布，优化用于升压提供给存储单元阵列的存储单元的写入电压和写入时间的电压电平。升压电路提高写入电压以供给存储单元。计数器根据定时器的信号对写入次数进行计数。定时器输出用于对从计数器计数预定写入次数的第一写入时间到任意写入时间之间的固定间隔计数写入时间的信号，并以一定间隔对写入次数进行计数，在任意写入时间之后，写入次数逐渐增加，以便控制向存储单元提供写入电压的时间。此外，电压控制电路根据升压电路根据任意的写入次数逐渐分割升压电平，直到写入电压达到预定上限，并且当写入电压达到预定上限时保持写入电压。

5. 发明授权

US6122193A Non-volatile semiconductor memory capable of storing 1-bit data or multi-bit data 有权
标题翻译：能够存储1位数据或多位数据的非易失性半导体存储器
公开(公告)号：US6122193A
公开(公告)日：2000-09-19
申请号：US323455
申请日：1999-06-01
申请人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
发明人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C2211/5641 , G11C2211/5642
摘要： Data latch circuits are provided corresponding to select memory cells from or into which read or program is executed. The data latch circuits are grouped by two into sets. When 2-bit data is read from or programmed into the select memory cells, one data latch circuit is selected by a select signal, and, when 1-bit data is read or programmed, the two data latch circuits in one set are selected by a select signal. Between one or two selected data latch circuits and a data input/output buffer, data is exchanged. By so doing, changeover between 2-level data and multi-level (4-level or more-level) data concerning program or read of data into or out the memory cells becomes possible.
摘要翻译：数据锁存电路是从执行读取或程序的选择存储器单元提供的。数据锁存电路分为两组。当2位数据从选择存储单元读取或编程到选择存储单元中时，通过选择信号选择一个数据锁存电路，当读取或编程1位数据时，一组中的两个数据锁存电路由选择信号。在一个或两个选择的数据锁存电路和数据输入/输出缓冲器之间，交换数据。通过这样做，有可能在二级数据与有关程序的多级（4级或更多级）数据之间切换或将数据读入或取出存储单元变成可能。

6. 发明授权

US06331945B1 Non-volatile semiconductor memory capable of storing one-bit data or multi-bit data 有权
标题翻译：能够存储一位数据或多位数据的非易失性半导体存储器
公开(公告)号：US06331945B1
公开(公告)日：2001-12-18
申请号：US09528112
申请日：2000-03-17
申请人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
发明人： Noboru Shibata , Tomoharu Tanaka , Hiroto Nakai , Toshio Yamamura , Susumu Fujimura
IPC分类号： G11C1606
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C2211/5641 , G11C2211/5642
摘要： Data latch circuits are provided corresponding to select memory cells from or into which read or program is executed. The data latch circuits are grouped by two into sets. When 2-bit data is read from or programmed into the select memory cells, one data latch circuit is selected by a select signal, and, when 1-bit data is read or programmed, the two data latch circuits in one set are selected by a select signal. Between one or two selected data latch circuits and a data input/output buffer, data is exchanged. By so doing, changeover between 2-level data and multi-level (4-level or more-level) data concerning program or read of data into or out the memory cells becomes possible.
摘要翻译：数据锁存电路是从执行读取或程序的选择存储器单元提供的。数据锁存电路分为两组。当2位数据从选择存储单元读取或编程到选择存储单元中时，通过选择信号选择一个数据锁存电路，当读取或编程1位数据时，一组中的两个数据锁存电路由选择信号。在一个或两个选择的数据锁存电路和数据输入/输出缓冲器之间，交换数据。通过这样做，有可能在二级数据与有关程序的多级（4级或更多级）数据之间切换或将数据读入或取出存储单元变成可能。

7. 发明授权

US5615148A Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US5615148A
公开(公告)日：1997-03-25
申请号：US622088
申请日：1996-03-26
申请人： Toshio Yamamura , Hiroto Nakai
发明人： Toshio Yamamura , Hiroto Nakai
IPC分类号： G11C16/16 , G11C29/52 , G11C11/34
CPC分类号： G11C16/16 , G11C29/52
摘要： EEPROM for directly outputting addresses of those in which erasing failure occurs among a plurality of blocks to be erased for erasing by a plural block simultaneous erasing system to an outside of a chip and enabling a system side to directly identify the addresses thereof is provided with a plurality of cell blocks each having an array of nonvolatile memory cells, plural block simultaneous erasing control arrangement for performing cell data erasing from a plurality of cell blocks specified as to be erased for simultaneous data erasing and a block address outputting circuit for outputting, when existence of erase failure blocks is detected after block simultaneous erasing, addresses thereof to the outside of the chip.
摘要翻译： EEPROM将用于通过多个块同时擦除系统擦除的多个要擦除的块中的擦除失败的地址的地址直接输出到芯片的外部并使系统侧能够直接识别其地址的EEPROM被提供有多个具有非易失性存储单元阵列的单元块，多个块同时擦除控制装置，用于执行从指定为被擦除同时擦除的多个单元块中擦除的单元数据;以及块地址输出电路，用于当存在时在块同时擦除之后检测到擦除失败块，其地址到芯片的外部。

8. 发明授权

US08477541B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
公开(公告)号：US08477541B2
公开(公告)日：2013-07-02
申请号：US13489977
申请日：2012-06-06
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

9. 发明授权

US07916555B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
标题翻译：半导体集成电路适用于输出内部操作的通过/失败结果
公开(公告)号：US07916555B2
公开(公告)日：2011-03-29
申请号：US12252896
申请日：2008-10-16
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

10. 发明授权

US07301834B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07301834B2
公开(公告)日：2007-11-27
申请号：US10694861
申请日：2003-10-29
申请人： Hiroshi Nakamura , Toshio Yamamura
发明人： Hiroshi Nakamura , Toshio Yamamura
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C5/025 , G11C16/0483 , G11C16/3445 , G11C16/3459
摘要： A plurality of memory cell arrays Array0, Array1, Array2, Array3, Array4, Array5, Array6 and Array7 which can perform a parallel operation are arranged in a later generation chip. Each of the memory cell arrays Array0 and Array4, the memory cell arrays Array1 and Array5, the memory cell arrays Array2 and Array6, and the memory cell arrays Array3 and Array7 constitutes one cell array group. A Pass/Fail signal indicative of success or failure of the operation is outputted in accordance with each cell array group. It is good to make the number of cell array groups equal to the number of memory cell arrays or the number of cell array groups of a precedent generation chip.
摘要翻译：可以执行并行操作的多个存储单元阵列阵列0，阵列1，阵列2，阵列3，阵列4，阵列5，阵列6和阵列7被布置在后一代芯片中。存储单元阵列Array 0和阵列4，存储单元阵列阵列1和阵列5，存储单元阵列阵列2和阵列6以及存储单元阵列阵列3和阵列7中的每一个构成一个单元阵列组。根据每个单元阵列组输出指示操作成功或失败的通过/失败信号。使单元阵列组的数量等于存储单元阵列的数量或先前代码芯片的单元阵列组的数量是很好的。

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