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1. 发明授权

US07428667B2 Method and device for interleaving and method and device for de-interleaving 有权
标题翻译：用于交织的方法和装置以及用于解交织的方法和装置
公开(公告)号：US07428667B2
公开(公告)日：2008-09-23
申请号：US11540059
申请日：2006-09-29
申请人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
发明人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
IPC分类号： G06F11/00
CPC分类号： H04L1/0071 , H03M13/00 , H03M13/27 , H03M13/2703 , H03M13/2707 , H03M13/2764 , H03M13/2792 , H03M13/35 , H03M13/356 , H04L1/0009 , H04L1/0025 , H04L1/007 , H04L1/0072 , H04L1/0088
摘要： The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately supplies to the operating memory 220 a plurality of addresses for reading a plurality of continuous bits corresponding to the header H from the operating memory 220, and an address for reading 1 bit corresponding to the data D from the operating memory 220, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.
摘要翻译：写地址提供部分210将写入地址用于写入与要发送或存储的帧中包含的标题H相对应的位序列的位和与数据D对应的位序列的位写入到操作存储器220中。读取地址提供部件230从操作存储器220交替地向操作存储器220提供用于读取对应于头部H的多个连续位的多个地址，以及从操作中读取与数据D对应的1位的地址存储器220，并且读取比特序列，使得形成与头部H相对应的比特序列的比特被分散并布置在从操作存储器形成数据D的比特序列中。根据这种交织装置，可以根据其构成数据单独地随机化帧，并且可以以最适合于所述数据的格式来发送构成这样的数据的比特。

2. 发明授权

US07191369B2 Method and device for interleaving and method and device for de-interleaving 有权
标题翻译：用于交织的方法和装置以及用于解交织的方法和装置
公开(公告)号：US07191369B2
公开(公告)日：2007-03-13
申请号：US10885992
申请日：2004-07-06
申请人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
发明人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
IPC分类号： G06F11/00 , G06F12/16
CPC分类号： H04L1/0071 , H03M13/00 , H03M13/27 , H03M13/2703 , H03M13/2707 , H03M13/2764 , H03M13/2792 , H03M13/35 , H03M13/356 , H04L1/0009 , H04L1/0025 , H04L1/007 , H04L1/0072 , H04L1/0088
摘要： The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately supplies to the operating memory 220 a plurality of addresses for reading a plurality of continuous bits corresponding to the header H from the operating memory 220, and an address for reading 1 bit corresponding to the data D from the operating memory 220, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.
摘要翻译：写地址提供部分210将写入地址用于写入与要发送或存储的帧中包含的标题H相对应的位序列的位和与数据D对应的位序列的位写入到操作存储器220中。读取地址提供部件230从操作存储器220交替地向操作存储器220提供用于读取对应于头部H的多个连续位的多个地址，以及从操作中读取与数据D对应的1位的地址存储器220，并且读取比特序列，使得形成与头部H相对应的比特序列的比特被分散并布置在从操作存储器形成数据D的比特序列中。根据这种交织装置，可以根据其构成数据单独地随机化帧，并且可以以最适合于所述数据的格式来发送构成这样的数据的比特。

3. 发明授权

US06871302B1 Method and device for interleaving and method and device for deinterleaving 有权
标题翻译：用于交织的方法和装置以及用于解交织的方法和装置
公开(公告)号：US06871302B1
公开(公告)日：2005-03-22
申请号：US09462773
申请日：1999-05-27
申请人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
发明人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
IPC分类号： H03M13/00 , H03M13/27 , H03M13/35 , H04L1/00 , H04N19/895 , G06F11/00
CPC分类号： H04L1/0071 , H03M13/00 , H03M13/27 , H03M13/2703 , H03M13/2707 , H03M13/2764 , H03M13/2792 , H03M13/35 , H03M13/356 , H04L1/0009 , H04L1/0025 , H04L1/007 , H04L1/0072 , H04L1/0088
摘要： The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately supplies to the operating memory 220 a plurality of addresses for reading a plurality of continuous bits corresponding to the header H from the operating memory 220, and an address for reading 1 bit corresponding to the data D from the operating memory 220, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.
摘要翻译：写入地址提供部分210将写入地址用于写入与要发送或存储的帧中包含的标题H相对应的比特序列的位和对应于数据D的比特序列到写入地址提供部分210中。读取地址提供部分 230交替地向操作存储器220提供用于从操作存储器220读取对应于头部H的多个连续位的多个地址和用于从操作存储器220读取对应于数据D的1位的地址，并且读取比特序列使得形成对应于标题H的比特序列的比特被分散并布置在从操作存储器形成数据D的比特序列内。根据这种交织装置，可以根据其构成数据单独地随机化帧，并且可以以最适合于所述数据的格式来发送构成这样的数据的比特。

4. 发明授权

US07469365B2 Method and device for interleaving and method and device for de-interleaving 有权
标题翻译：用于交织的方法和装置以及用于解交织的方法和装置
公开(公告)号：US07469365B2
公开(公告)日：2008-12-23
申请号：US11541228
申请日：2006-09-29
申请人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
发明人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
IPC分类号： G06F11/00 , G06F12/16
CPC分类号： H04L1/0071 , H03M13/00 , H03M13/27 , H03M13/2703 , H03M13/2707 , H03M13/2764 , H03M13/2792 , H03M13/35 , H03M13/356 , H04L1/0009 , H04L1/0025 , H04L1/007 , H04L1/0072 , H04L1/0088
摘要： The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately supplies to the operating memory 220 a plurality of addresses for reading a plurality of continuous bits corresponding to the header H from the operating memory 220, and an address for reading 1 bit corresponding to the data D from the operating memory 220, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.
摘要翻译：写入地址提供部分210将写入地址用于写入与要发送或存储的帧中包含的标题H相对应的比特序列的位和对应于数据D的比特序列到写入地址提供部分210中。读取地址提供部分 230交替地向操作存储器220提供用于从操作存储器220读取对应于头部H的多个连续位的多个地址和用于从操作存储器220读取对应于数据D的1位的地址，并且读取比特序列使得形成对应于标题H的比特序列的比特被分散并布置在从操作存储器形成数据D的比特序列内。根据这种交织装置，可以根据其构成数据单独地随机化帧，并且可以以最适合于所述数据的格式来发送构成这样的数据的比特。

5. 发明申请

US20050005223A1 Method and device for interleaving and method and device for de-interleaving 有权
标题翻译：用于交织的方法和装置以及用于解交织的方法和装置
公开(公告)号：US20050005223A1
公开(公告)日：2005-01-06
申请号：US10885992
申请日：2004-07-06
申请人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
发明人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
IPC分类号： H03M13/00 , H03M13/27 , H03M13/35 , H04L1/00 , H04N19/895
CPC分类号： H04L1/0071 , H03M13/00 , H03M13/27 , H03M13/2703 , H03M13/2707 , H03M13/2764 , H03M13/2792 , H03M13/35 , H03M13/356 , H04L1/0009 , H04L1/0025 , H04L1/007 , H04L1/0072 , H04L1/0088
摘要： The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately supplies to the operating memory 220 a plurality of addresses for reading a plurality of continuous bits corresponding to the header H from the operating memory 220, and an address for reading 1 bit corresponding to the data D from the operating memory 220, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.
摘要翻译：写入地址提供部分210将写入地址用于写入与要发送或存储的帧中包含的标题H相对应的比特序列的位和对应于数据D的比特序列到写入地址提供部分210中。读取地址提供部分 230交替地向操作存储器220提供用于从操作存储器220读取对应于头部H的多个连续位的多个地址和用于从操作存储器220读取对应于数据D的1位的地址，并且读取比特序列使得形成对应于标题H的比特序列的比特被分散并布置在从操作存储器形成数据D的比特序列内。根据这种交织装置，可以根据其构成数据单独地随机化帧，并且可以以最适合于所述数据的格式来发送构成这样的数据的比特。

6. 发明授权

US06738393B2 Frame synchronization circuit 失效
标题翻译：帧同步电路
公开(公告)号：US06738393B2
公开(公告)日：2004-05-18
申请号：US09171216
申请日：1998-10-13
申请人： Toshio Miki , Sanae Hotani
发明人： Toshio Miki , Sanae Hotani
IPC分类号： H04J307
CPC分类号： H04J3/0608 , H04L7/08
摘要： In a frame synchronization circuit, which prevents the occurrence of synchronous error due to a data loss/insertion while restraining a false synchronization/out of synchronization based on typical code error in a conventional data transmission system, the frame synchronization circuit is provided with a frame synchronization code detector which detects a frame synchronization code from a received data sequence to output a frame position and outputs a checked result by checking a frame synchronization code detected and a correct frame synchronization code. The frame synchronization circuit is also provided with and a data loss and data insertion period judgment circuit which determines which presumes whether a data loss or data insertion has occurred in the received data sequence according to the checked result.
摘要翻译：在帧同步电路中，根据常规数据传输系统中的典型代码错误，防止由于数据丢失/插入而导致的同步误差的发生同时抑制错误同步/失步，帧同步电路具有帧同步码检测器，其从接收的数据序列检测帧同步码以输出帧位置，并通过检查检测到的帧同步码和正确的帧同步码来输出检查结果。帧同步电路还具有数据丢失和数据插入周期判断电路，该电路根据检查结果确定哪个是假定在接收的数据序列中是否发生了数据丢失或数据插入。

7. 发明授权

US06434718B1 Error protection method and error protection device 有权
标题翻译：错误保护方法和错误保护装置
公开(公告)号：US06434718B1
公开(公告)日：2002-08-13
申请号：US09462800
申请日：2000-01-10
申请人： Toshiro Kawahara , Toshio Miki , Sanae Hotani
发明人： Toshiro Kawahara , Toshio Miki , Sanae Hotani
IPC分类号： H03M1335
CPC分类号： H04L1/0059 , H03M13/00 , H03M13/2703 , H03M13/2764 , H03M13/35 , H04L1/0009 , H04L1/0025 , H04L1/0061 , H04L1/007 , H04L1/0071 , H04L2001/0098
摘要： The frame-forming data computing part 101 sorts a plurality of types of parameters forming the frames, and generates frame-forming data that contains data relating to the configuration of said frames and data establishing for each class the error protection method to be applied to each said parameter. The frame-forming data error protection processing part 102 implements the specified error protection for said frame-forming data. The class data error protection processing part 103 implements error protection that is specified for each class according to the frame-forming data, with respect to the parameters that are sorted into a plurality of classes. The synthesizer 104 transmits the frame-forming data that has undergone the specified error protection and the parameters that have undergone the error protection established for each class. In accordance with the present invention, error correction is implemented on frame-forming data indicating the configuration of the frames, and it is also implemented on each class according to the frame-forming data, and these two are synthesized and output. Therefore, it becomes possible to obtain data relating to the configuration of said frames, according to frame-forming data received by the receiving side device. As a result, it is possible to set on the transmission side as desired the content of the error protection to be applied to each class, and in addition, error protection becomes possible for each frame, due to the fact that these data are contained in the frame-forming data, even if the frame has a variable frame length, with the number of bits fluctuating over time.
摘要翻译：帧形成数据计算部分101对形成帧的多种参数进行排序，并且生成包含与所述帧的配置相关的数据的帧形成数据和为每个类建立的数据，将要应用于每个类的错误保护方法说参数。帧形成数据错误保护处理部分102对所述帧形成数据实施指定的错误保护。类数据错误保护处理部分103针对分类为多个类别的参数，根据帧形成数据实现针对每个类指定的错误保护。合成器104发送已经经历了指定的错误保护的帧形成数据和为每个类建立的已经经历了错误保护的参数。根据本发明，在指示帧的配置的帧形成数据上实现纠错，并且还根据帧形成数据在每个类上实现这两个，并且这两个被合成和输出。因此，根据由接收侧装置接收到的帧形成数据，可以获得与所述帧的配置有关的数据。结果，可以根据需要在发送侧设置要应用于每个类的错误保护的内容，并且另外，由于这些数据被包含在每个帧中，因此每个帧都可以进行错误保护帧形成数据，即使帧具有可变帧长度，随着时间间隔而变化的位数。

8. 发明授权

US5953378A Frame synchronization circuit and communications system 失效
标题翻译：帧同步电路和通信系统
公开(公告)号：US5953378A
公开(公告)日：1999-09-14
申请号：US934296
申请日：1997-09-19
申请人： Sanae Hotani , Toshirou Kawahara , Toshio Miki
发明人： Sanae Hotani , Toshirou Kawahara , Toshio Miki
IPC分类号： H04J3/06 , H04L1/00 , H04L7/04 , H03D1/00
CPC分类号： H04L1/0047 , H04J3/0608 , H04L1/0046 , H04L7/048 , H04L1/0007 , H04L1/0009 , H04L1/0057 , H04L1/0061
摘要： Likelihood calculating circuit A1 calculates the hamming distance between a received data series and a unique word as likelihood data d1. Likelihood calculating circuit A2 calculates the number of transmission errors using redundant data, and outputs this value as likelihood data d2. Likelihood data d1,d2 are added at adding circuit 21, and the output thereof is compared to the threshold value of determination circuit with threshold 22. The results of this comparison are output as determination signal with threshold DT. Synchronous determination circuit 23 generates a synchronous determination signal SD based on determination signal with threshold DT. Accordingly, the present invention provides a frame synchronization circuit in which it is possible to avoid out of synchronization or false synchronization, without increasing the amount of redundancy necessary to detect frame synchronization.
摘要翻译：似然计算电路A1计算接收数据序列与唯一字之间的汉明距离作为似然数据d1。似然计算电路A2使用冗余数据计算发送错误的数量，并将该值作为似然数据d2输出。在加法电路21中加上似然数据d1，d2，并将其输出与阈值为22的判定电路的阈值进行比较。该比较的结果作为具有阈值DT的判定信号输出。同步确定电路23基于具有阈值DT的确定信号产生同步确定信号SD。因此，本发明提供了一种帧同步电路，其中可以避免不同步或错误同步，而不增加检测帧同步所需的冗余量。

9. 发明申请

US20070038903A1 Method and device for interleaving and method and device for de-interleaving 有权
标题翻译：用于交织的方法和装置以及用于解交织的方法和装置
公开(公告)号：US20070038903A1
公开(公告)日：2007-02-15
申请号：US11541228
申请日：2006-09-29
申请人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
发明人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
IPC分类号： G06F11/00
CPC分类号： H04L1/0071 , H03M13/00 , H03M13/27 , H03M13/2703 , H03M13/2707 , H03M13/2764 , H03M13/2792 , H03M13/35 , H03M13/356 , H04L1/0009 , H04L1/0025 , H04L1/007 , H04L1/0072 , H04L1/0088
摘要： The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately supplies to the operating memory 220 a plurality of addresses for reading a plurality of-continuous bits corresponding to the header H from the operating memory 220, and an address for reading 1 bit corresponding to the data D from the operating memory 220, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.
摘要翻译：写地址提供部分210将写入地址用于写入与要发送或存储的帧中包含的标题H相对应的位序列的位和与数据D对应的位序列的位写入到操作存储器220中。读取地址提供部件230向操作存储器220交替地提供用于从操作存储器220读取与头部H相对应的多个连续位的多个地址，以及从该存储器220读取对应于数据D的1位的地址操作存储器220，并且读取比特序列，使得形成与头部H相对应的比特序列的比特被分散并布置在从操作存储器形成数据D的比特序列中。根据这种交织装置，可以根据其构成数据单独地随机化帧，并且可以以最适合于所述数据的格式来发送构成这样的数据的比特。

10. 发明申请

US20070038902A1 Method and device for interleaving and method and device for de-interleaving 有权
标题翻译：用于交织的方法和装置以及用于解交织的方法和装置
公开(公告)号：US20070038902A1
公开(公告)日：2007-02-15
申请号：US11540059
申请日：2006-09-29
申请人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
发明人： Toshiro Kawahara , Toshio Miki , Sanae Hotani , Takashi Suzuki
IPC分类号： G06F11/00
CPC分类号： H04L1/0071 , H03M13/00 , H03M13/27 , H03M13/2703 , H03M13/2707 , H03M13/2764 , H03M13/2792 , H03M13/35 , H03M13/356 , H04L1/0009 , H04L1/0025 , H04L1/007 , H04L1/0072 , H04L1/0088
摘要： The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately supplies to the operating memory 220 a plurality of addresses for reading a plurality of continuous bits corresponding to the header H from the operating memory 220, and an address for reading 1 bit corresponding to the data D from the operating memory 220, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.
摘要翻译：写入地址提供部分210将写入地址用于写入与要发送或存储的帧中包含的标题H相对应的比特序列的位和对应于数据D的比特序列到写入地址提供部分210中。读取地址提供部分 230交替地向操作存储器220提供用于从操作存储器220读取对应于头部H的多个连续位的多个地址和用于从操作存储器220读取对应于数据D的1位的地址，并且读取比特序列使得形成对应于标题H的比特序列的比特被分散并布置在从操作存储器形成数据D的比特序列内。根据这种交织装置，可以根据其构成数据单独地随机化帧，并且可以以最适合于所述数据的格式来发送构成这样的数据的比特。

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